Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2007-08-21
2007-08-21
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S374000
Reexamination Certificate
active
10920579
ABSTRACT:
A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.
REFERENCES:
patent: 4180416 (1979-12-01), Brock
patent: 4470062 (1984-09-01), Muramatsu
patent: 4502914 (1985-03-01), Trumpp et al.
patent: 4624046 (1986-11-01), Shideler
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4819052 (1989-04-01), Hutter
patent: 4824797 (1989-04-01), Goth
patent: 4839301 (1989-06-01), Lee
patent: 4879679 (1989-11-01), Kikuda et al.
patent: 4980747 (1990-12-01), Hutter et al.
patent: 5073509 (1991-12-01), Lee
patent: 5087586 (1992-02-01), Chan et al.
patent: 5128274 (1992-07-01), Yabu et al.
patent: 5173438 (1992-12-01), Sandhu
patent: 5179038 (1993-01-01), Kinney et al.
patent: 5191509 (1993-03-01), Wen
patent: 5302233 (1994-04-01), Kim et al.
patent: 5356828 (1994-10-01), Swan et al.
patent: 5358894 (1994-10-01), Fazan et al.
patent: 5366590 (1994-11-01), Kadomura
patent: 5429995 (1995-07-01), Nishiyama et al.
patent: 5470783 (1995-11-01), Chiu et al.
patent: 5492736 (1996-02-01), Laxman et al.
patent: 5530293 (1996-06-01), Cohen et al.
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5702976 (1997-12-01), Schuegraf et al.
patent: 5859466 (1999-01-01), Wada
patent: 5914523 (1999-06-01), Bashir et al.
patent: 6781212 (2004-08-01), Kao et al.
patent: 0 220 108 (1987-04-01), None
patent: 62131539 (1987-06-01), None
patent: 01138730 (1989-05-01), None
patent: 09064164 (1997-03-01), None
Kikuyo Ohe, S. Odanaka, K. Moriyama, T. Hori, G. Fuse, “Narrow-Width Effects of Shallow Trench-Isolated CMOS with n+-Polysilicon Gate”, IEEE Transactions on Electron Devices, vol. 36, No. 6, (Jun. 1989).
S.M. Sze, “Semiconductor Devices-Physics and Technology”, pp. 195-197 (1985).
Stanley Wolf,Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, CA, pp. 12-83 (1990).
Kirk-Othmer,Encyclopedia of Chemical Technology, vol. 2, 2ndEd. 1967, pp. 791-792.
S.M. Sze, “Physics of Semiconductor Devices”, John Wiley & Sons, 1981, XP002130269, p. 397, Figure 28.
Kao David Y.
Yang Rongsheng
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
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