Selective test point for high speed SERDES cores in...

Multiplex communications – Diagnostic testing – Fault detection

Reexamination Certificate

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C370S248000

Reexamination Certificate

active

07855969

ABSTRACT:
The present invention is directed to a method and system for testing systems involving high speed SERDES cores by exposing an internal nature of signals. The signals are tapped at various external test points. The present invention may take one or more test points in receive and/or transmit paths of high speed SERDES cores, and expose the test points by routing signals to the pins/balls on a chip. Programmable directing (multiplexing) of signals may be utilized to restrict number of output debug ports. Consequently, the number of the pin count required for the chip may be controlled.

REFERENCES:
patent: 4821269 (1989-04-01), Jackson et al.
patent: 5732209 (1998-03-01), Vigil et al.
patent: 6252912 (2001-06-01), Salinger
patent: 6782336 (2004-08-01), Shah
patent: 7114135 (2006-09-01), Gauvin
patent: 2002/0053056 (2002-05-01), Kuegler et al.
patent: 2005/0193302 (2005-09-01), Arguelles et al.
“SerDes core supports 155Mbps to 3.125Gbps”, EE Times Asia, Dec. 29, 2004.

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