Selective T-gate process

Details Selective T-gate process Selective T-gate process

2000-08-23

2003-02-25

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Forming schottky junction

Compound semiconductor

C438S577000, C438S579000, C438S670000, C438S182000

Reexamination Certificate

active

06524937

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the selective fabrication of T-shaped metal structures and more particularly relates to the selective fabrication of T-shaped gates for field-effect transistors.
BACKGROUND OF THE INVENTION
As microwave communication technology moves forward, communication frequencies tend to shift toward higher frequency bands. Devices made of conventional silicon are suitable for applications below 2 GHz. For applications above 2 GHz, however, the devices typically are made of compound semiconductors such as GaAs- or InP-based materials, because GaAs, InP, and related compound semiconductors have electron mobilities that are higher than conventional silicon compounds.
Typically, field-effect transistors (FETs) in radio frequency and microwave circuits have short gate lengths (e.g., gate lengths that are smaller than 1 micron). Such devices have higher device gains and cutoff frequencies than their counterparts with longer gate lengths, primarily due to the lower gate-source capacitance and higher transconductance associated with shorter gate lengths. In addition, submicron gatelength devices have better noise characteristics.
As the length of the gate is reduced, however, its cross sectional area is also reduced, and the resistance of the gate is increased. High gate resistance is particularly detrimental to an FET during high-frequency operation. Effects of high gate resistance include a reduction in high-frequency device gain, current gain cutoff frequency and power gain cut-off frequency.
One way to address this trade-off between gate length and gate cross section is to provide the FET with a T-shaped gate (also frequently referred to as a “mushroom gate”). Procedures for forming gates of this type have been proposed in the prior art, several of which are disclosed in U.S. Pat. No. 5,766,967, the entire disclosure of which is hereby incorporated by reference.
Such gates (frequently referred to as the “gate finger”) have a distinct undercut feature at the semiconductor surface, giving the gate its “T-shaped” appearance. This undercut feature minimizes gate length, while at the same time retaining a relatively large overall gate cross-sectional area. The undercut feature, however, is not desirable in connection with other metal features that are frequently deposited at the same time as the gate finger itself, such as manifolds and gate interconnect structures. In particular, this undercutting frequently results in poor step coverage (i.e., poor metal continuity) for subsequent overlay metals, resulting in decreased product reliability.
This prior art problem is illustrated in
FIG. 1
, which shows a T-shaped gate finger
12
on a substrate
18
. Also shown is an adjacent T-shaped gate interconnect
14
with associated overlay metal
16
. Both the T-shaped gate finger
12
and the T-shaped gate interconnect
14
are provided with substantial undercutting at the semiconductor interface. This undercutting is desirable in connection with the T-shaped gate finger
12
for the reasons set forth above. It is undesirable, however, in connection with the T-shaped gate interconnect
14
upon which the overlay metal
16
is applied. Specifically, as seen in
FIG. 1
, the undercutting associated with the T-shaped interconnect
14
can result in a discontinuity
20
(i.e., a void) within the overlay metal
16
, reducing device reliability.
SUMMARY OF THE INVENTION
The above and other problems associated with the prior art are overcome by the present invention. According to one embodiment of the invention, a process is provided, along with a field effect transistor with a T-shaped gate formed by this process. The process comprises:
a) providing a doped semiconductor substrate comprising source electrodes and gate electrodes;
b) forming lower photoresist features having rounded shoulders over the source electrodes and the gate electrodes on the substrate;
c) forming a plurality of upper photoresist features over the lower photoresist features, wherein the upper photoresist features have undercut sides, and wherein the upper photoresist features comprise: (i) edges that do not extend to edges of the lower photoresist features, thereby leaving portions of the rounded shoulders uncovered and (ii) edges that extend beyond edges of the lower photoresist features, thereby covering portions of the substrate;
d) forming gate metal features and interconnect metal features (preferably in a single step) over the substrate, wherein the gate metal features comprise edges that extend beyond the substrate and terminate over the rounded shoulders, and wherein the interconnect metal features have edges that do not extend beyond the substrate; and
e) removing the lower photoresist features and the upper photoresist features (preferably by dissolution) to produce a structure in which (i) the gate metal features have sides that are undercut at the substrate and (ii) the interconnect metal features do not have sides that are undercut at the substrate.
Preferably, the lower photoresist features are formed by a process comprising: applying a lower layer of photoresist; patterning the lower layer of photoresist to form a plurality of lower photoresist features; and heating the lower photoresist features (e.g., to 120-180° C.) such that edge portions of the lower photoresist features flow to form the rounded shoulders. Preferred materials for the lower layer of photoresist are positive photoresists.
The upper photoresist features are preferably formed by a process comprising: applying an upper layer of photoresist; and photolithographically forming the upper photoresist features. Prior to application of the upper photoresist layer, it is typically preferred to treat the lower photoresist features such that the dimensions of the lower photoresist features are stable upon subsequent application of the upper photoresist layer. Preferred processes for treating the lower photoresist features include (i) treatments comprising crosslinking (e.g., using deep ultraviolet light) surface portions of the lower photoresist features and (ii) treatments comprising the formation of a barrier layer (e.g., a metal, a metal oxide, or polymer precursors) that covers the lower photoresist features.
According to another embodiment of the invention, a process is provided, along with a field effect transistor constructed in accordance with this process. The process comprises:
a) providing a doped semiconductor substrate comprising source electrodes and gate electrodes;
b) applying a lower layer of photoresist over the source electrodes, the gate electrodes and the substrate;
c) patterning the lower layer of photoresist to form a plurality of lower photoresist features over the source electrodes and the gate electrodes;
d) heating the lower photoresist features such that edge portions of the lower photoresist features flow to form rounded shoulders;
e) treating the lower photoresist features such that dimensions of the lower photoresist features are stable upon application of an upper photoresist layer;
f) applying the upper layer of photoresist over the treated lower photoresist features;
g) photolithographically forming from the upper layer of photoresist a plurality of upper photoresist features over the lower photoresist features, wherein the upper photoresist features have undercut sides, and wherein the upper photoresist features comprise (i) edges that do not extend to edges of the lower photoresist features, leaving portions of the rounded shoulders uncovered and (ii) edges that extend beyond edges of the lower photoresist features, covering portions of the substrate;
h) conducting a metal deposition step such that temporary metal features are formed over the upper photoresist features, and such that gate and interconnect metal features are formed over the substrate, wherein the gate metal features comprise edges that extend beyond the substrate and terminate over the rounded shoulders, and wherein the interconnect metal features have edges that do not extend beyond the substrate; and
i) di

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