Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-01-29
2008-01-29
Lam, David (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185280, C365S185190, C365S185210
Reexamination Certificate
active
07324383
ABSTRACT:
A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vtof the cell. The other cells continue to be programmed at their normal pace. As the Vtfor each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.
REFERENCES:
patent: 6611460 (2003-08-01), Lee et al.
patent: 6643188 (2003-11-01), Tanaka et al.
patent: 6803630 (2004-10-01), Pio et al.
patent: 6888758 (2005-05-01), Hemink et al.
patent: 7031198 (2006-04-01), Kanai
patent: 7068539 (2006-06-01), Guterman et al.
patent: 2004/0066685 (2004-04-01), Choi
Incarnati Michele
Santin Giovanni
Vali Tommaso
Lam David
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
LandOfFree
Selective slow programming convergence in a flash memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective slow programming convergence in a flash memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective slow programming convergence in a flash memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2766200