Selective seed and plate using permanent resist

Details Selective seed and plate using permanent resist Selective seed and plate using permanent resist

1998-03-17

2001-07-24

Gulakowski, Randy (Department: 1746)

Etching a substrate: processes

Forming groove or hole in a substrate which is subsequently...

C216S017000, C216S018000, C216S020000, C216S034000, C216S035000, C216S038000, C216S049000, C216S100000, C216S108000, C216S052000, C216S053000, C216S088000, C427S097100, C427S098300

Reexamination Certificate

active

06264851

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of microelectronics (e.g., integrated circuits and printed circuit boards), and more particularly to compositions and methods for etching materials from the upper surface of resist layers previously applied to silicon or polymer substrates for the purpose of creating fine-line conductive lines on integrated circuits or circuit boards.
BACKGROUND OF THE INVENTION
Fine-line conductive lines must be manufactured for PC boards and cards with high quality, especially with regard to potential defects such as short or open circuits. These defects cause significant waste and are increasingly a problem as the line width becomes narrower and the density of these lines increases on the substrate. As is understood in the industry, the creation of discrete, fine conductive lines requires the formation of discontinuous areas, yet the conductive materials are typically applied in the form of a continuous, uniform layer via a process such as sputtering or electrolytic deposition. To convert this uniform layer into discontinuous areas, a process such as etching is typically required at some point during manufacturing.
The conductive lines can be created by either an additive or a subtractive process. When the subtractive process is employed, the conductive layer is applied to the substrate followed by a uniform application of resist material. The resist material is subsequently imaged and developed to form discontinuous areas on the conductive layer. The areas of the conductive layer that are uncovered by this process can be chemically etched, leaving a resist-covered fine line or pattern. Removal of the remaining resist creates the final coated substrate.
This process is complicated by a number of factors. For example, manufacture of high resolution printed wire boards cannot easily achieve sufficient resolution and bonding to the substrate laminate. The photoresist imaging step further requires that the conductive layer be free of minute scratches which could cause the photoresist to bridge over the top and thereby be undercut by the etchant. significantly, most of the conductive material foil initially applied must be etched away, causing significant waste handling problems. Furthermore, since the etching process is not completely anisotropic, the conductive fine lines can be undercut causing potential adhesion problems.
For the reasons cited hereinabove, the prior art has beneficiently utilized the process of additive circuitry. For example, additive circuits have been formed on an insulated, generally flat panel substrate, wherein the unclad substrate is electroless plated overall with a thin conductive layer, then photopatterned with a plating resist pattern covering part of the plating to define the primary circuit wiring pattern. The exposed plating is then electroplated to increase the thickness of the conductors. The conductors are then permanently defined by removing the plating resist and etching the thin electroless copper now resident between the conductor fine lines. This type of process is known as semi-additive, in that electroplating is used.
Fully additive circuits have been made in the prior art by using a seeded flat panel substrate laminate, which catalyzes that insulation, making it receptive to electroless copper deposition, thereby permitting conductors to be formed by imaging a permanent plating resist onto the substrate laminate. When electroless plated, the conductors are formed on the substrate laminate only where not covered by the resist. This process eliminates several of the problems associated with the subtractive process, but still requires etching of the seed layer.
One significant limitation for the production of fine-line conductive lines is the fragility of the conductive layer tracing and its susceptibility to damage from handling during manufacturing. The etching process is the most likely cause of such damage, since it is typically performed by mechanical grinding or using harsh chemical etchants. These processes, especially mechanical grinding, create debris that can cause shorting of the circuits if proper cleaning is not employed, or can create open circuits if the grinding cuts through the fine lines or causes delamination. It is understood that the thinner the layer to be etched or the milder the conditions of the etching process, the less likely will these defects occur. Therefore, there is an ongoing desire for improvements in this process.
The conductive layer and subsequently derived fine lines and patterns are typically made using copper metal. However, copper provides poor adhesion to substrates such as silicon or silicon dioxide wafers or polymer substrates. This is especially the case if dirt, scratches, or undercutting occurs. In these situations there is a likelihood of generating open circuits. To correct this defect, additional steps are performed, involving depositing a seed layer. Prior art references cite reactive metals such as palladium or chromium for this application, but these metals are expensive.
It can therefore be seen that there is a need in the art for a process to produce printed circuit boards and integrated circuits with a minimum number of steps, which process is cost efficient, environmentally nonhazardous and allows for the creation of high quality fine-line circuits having minimal circuit defects.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method has been developed wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.
The present invention provides a method for controllably and uniformly generating a thin seed layer over the surface of an imaged and developed photoresist-coated substrate base. The thin seed layer can be composed of various materials such as nickel, copper, cobalt, chromium or noble metals such as palladium. Methods for applying the seed layer in the instant invention are described in U.S. Pat. No. 3,993,799 issued to Feldstein; U.S. Pat. No. 3,783,005 issued to Kenney; U.S. Pat. Nos. 3,772,055 and 3,772,078 issued to Polichette et al; and U.S. Pat. No. 3,011,920 issued to Shipley. Since the present invention employs an additive process, minimal quantities of raw materials, especially copper, are required and therefore the process generates significantly less waste associated with etching the thick copper plating that is typically required in the subtractive process.
The present invention provides a method for selectively etching the seed layer covering a photoresist layer using a combination of mechanical grinding and chemical etching. Minimal grinding is required, since the seed layer is very thin compared to prior art electroplated layers. To assist and facilitate the removal of the seed layer, mild chemical etchants can also be employed. Since only minimal grinding is required, the impact to the environment is low.
The present invention provides a method that does not require a highly planar base substrate, since in the grinding process, elevated areas are easily removed, creating substantially planar topmost surfaces.
The present invention provides a circuit board that contains a high density of fine conductive pathways due to excellent adhesion of the conductive material to the seed layer. The prior art processes require a uniform seed layer to be deposited on the substrate. After subsequent steps to generate the copper lines, all remaining uncovered seed layer must be removed before further processing can occur (e.g., gold plating wirebond pads). This prior art process causes undercutting of the copper lines and is especially problematic as the line spacing becomes tighter. The present invention completely eliminates this part of the process since no seed layer is present between the copper lines, therefore only top surface etching is required and no undercutting can occur.
The present invention also

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