Selective reduction of sidewall slope on isolation edge

Details Selective reduction of sidewall slope on isolation edge Selective reduction of sidewall slope on isolation edge

1999-12-13

2001-05-08

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C430S005000, C430S325000, C438S947000

Reexamination Certificate

active

06228745

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Cross-reference to Related Patent Applications
This patent application is related to U.S. patent application Ser. No. 08/820,401 entitled “Asymmetrical Field Effect Transistor”, and U.S. Pat. No. 5,948,571 entitled “Asymmetrical Resist Sidewall”, both filed on the same day as the instant application and both being presently assigned to the assignee of the instant application and the disclosure of which is incorporated herein by reference. This application is further related to U.S. patent application Ser. No. 09/175,856 filed Oct. 20, 1998 entitled “Asymmetrical Resist Sidewall,” the same being a Divisional application of said U.S. Pat. No. 5,948,571.
2. Field of the Invention
This invention relates to trench bounded transistors, and in particular trench bounded metal oxide semiconductor (MOS), or complentary metal oxide semiconductor (CMOS), or silicon on insulator (SOI), field effect transistors.
3. Description of Related Art
In electronic component manufacture and in particular integrated circuit silicon wafer manufacturing, the key factor in delineating small patterns in the wafer is the shape of the resist pattern. The following description will be directed to integrated circuit silicon wafer manufacture and silicon devices but it will be appreciated by those skilled in the art that the invention may be applied to the manufacture of other electronic components such as gallium arsenide circuits, component packages and printed circuit boards. In the manufacture of integrated circuit components such as semiconductors, electronic circuit pattern control, e.g., linewidth control is becoming increasingly important because of even higher integration of the circuits and the linewidth and other circuit patterns are required to be increasingly fine and precise. Pattern control in photolithographic processes, however, is negatively impacted by numerous effects ranging from resist thickness variations, bake non-uniformities, non-flat wafers, etc. Photolithography techniques are preferably used to form the fine resist pattern to define the circuit and, in general, a wafer, on which a resist having a predetermined thickness is applied, is positioned on a wafer stage and light from a light source passes through a photo mask having a predetermined mask (circuit) pattern thereon. The light passing through the photo mask is projected onto the resist on the wafer forming the mask pattern on the resist. The resists are typically negative resists or positive resists. The exposed resist is then processed using a number of cleaning, developing and etching steps to form a pattern on the wafer either in the form of openings in the resist which are to be metallized to form the desired circuit pattern (negative resist) or in the form of a positive resist pattern delineating the desired pattern on the wafer surface to be metallized. The above photolithographic process is shown in U.S. Pat. No. 5,300,786 which is assigned to the assignee of the present invention.
In either of the negative or positive resist methods or combination resist methods (e.g., image reversal resists), it is necessary that a photo mask be used to form the pattern on the resist and, traditionally, the imaging process using optical lithography creates a plurality of resist patterns which are each, in cross-section, of substantially constant width, height and symmetry. Under some exposure conditions, the width of the resist pattern may vary somewhat with the height of the resist with the width at the base being slightly wider than the width at the top of the resist. In any event, the resist pattern is still symmetrical and a metallized circuit line would be of essentially constant cross-section measured about a vertical axis extending upward from the midpoint of the base of the resist pattern.
There are many different integrated circuit manufacturing processes that require an asymmetric resist pattern as part of the process to provide desired circuit designs, and one application, for example, is to produce a pattern for lift off processes. These methods are well known in the art. A number of attempts have been made to create an asymmetrical resist (photoresist) profile or pattern. In U.S. Pat. No. 5,547,789 to Nakatani et al. an asymmetrical light intensity profile is used to pattern a positive resist, which resist is then converted by flood illumination into a negative resist (image reversal resist) in order to affect the placement of subsequently formed gate electrodes. The purpose of the asymmetry of the resist pattern is to create an asymmetrical placement of the gate electrode. The asymmetrical intensity profile is achieved by a pattern transfer mask comprised of a transfer substrate, a linear light shielding film pattern disposed on the transparent substrate, and a means for reducing the intensity of light transmitted through a part of the mask on either side of the light shielding film pattern. The pattern transfer mask comprises a transparent substrate having different kinds of light attenuating films placed on the transparent substrate next to the light shielding pattern such as an opaque material, a light shielding film with different thicknesses or a semi-transparent film. The resist profiles shown are strongly re-entrant on both sides of the pattern which is not acceptable for many manufacturing methods. Another patent which shows an asymmetrical light intensity profile is U.S. Pat. No. 5,370,975 to Nakatani wherein the mask designed to create the asymmetrical light profile employs a phase shifter with an edge angle ranging from 70°-85° or 9.5°-110° or the phase shifter is shaped to be smoothly curved. In U.S. Pat. No. 5,300,786, supra, there is a description of a phase shift mask which can shift the intensity profile of the light for the purpose of determining and controlling the focus settings of an optical lithography exposure system. When there is a change in focus, the minimum point of the intensity profile is shifted to create an asymmetrical displacement of the photoresist pattern to the left or right direction. The intensity profile is asymmetric about the minimum intensity peak point and it is the asymmetric peak shift which creates a pattern placement error which is used in conjunction with other reference patterns to measure the focus as an overlay by an automated overlay error measurement tool.
In U.S. Pat. No. 5,368,962 to Hanyu et al. a photo mask is shown comprising a light shielding layer formed on a mask substrate and light transmission areas defined on the mask substrate by the light shielding areas. The light transmitting areas are divided with phase shifters.
The above patents are hereby incorporated by reference.
There are various devices known which make use of trenches (also referred to as trench-bounded structures) to provide for a separation and/or isolation of adjacent circuits. Such trench-bounded structures are employed in CMOS logic and memory products fabricated in either bulk or SOI substrates. The presence of the semiconductor corner in the active device region (active area) of a surface-channel trench bounded MOSFET, for example, results in a parasitic leakage current between source and drain diffusions. It has been found that the leakage current along the corner of the MOSFET results from a local lowering of the threshold voltage, due to the geometry of the device. The leakage current is the residual source to drain current when it is desired that the device be non-conducting (off condition), typically at V
qs
=0. The electric field at the semiconductor corner is enhanced by its small radius of curvature, resulting in reduced a corner threshold voltage. In addition to increased leakage current, the enhanced corner electric field results in degraded device reliability. The portion of the semiconductor substrate containing the MOSFET (exclusive of the bounding trenches) is referred to as the active area.
It has been discovered that the device off-current is sensitive to the sidewall angle of the active area. Trench bounded MOSFETs typically have si

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