Selective receiver for each processor in a multiple processor sy

Details Selective receiver for each processor in a multiple processor sy Selective receiver for each processor in a multiple processor sy

1991-07-01

1994-05-17

Richardson, Robert L.

Boots, shoes, and leggings

364229, 3642292, 364271, 3642712, 364DIG1, G06F 104

Patent

active

053136209

ABSTRACT:
Circuitry, and associated methodology in a parallel processing system for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus (60) provides an efficient, non-destructive data transfer and storage environment. This is effected by augmenting each processor with a global clock (31), state alignment circuit (41, 42, 43) to synchronize the processors with the global clock buffers (140, 240, 340) for storing data received off the bus, and circuitry (130, 230, 330) for selectively enabling the buffer to accept those segments of data having addresses allocated to the given processor. To ensure that processing states are aligned, each state alignment circuit inhibits incrementing of the global clock until each corresponding processor transceives necessary data over the bus. To avoid overwriting of data during bus conflicts, the buffers are arranged to store data on a first-in, first-out basis and to control the processing states and data transfer in correspondence to respective bus and processor states.

REFERENCES:
patent: 4494190 (1985-01-01), Peters
patent: 4663708 (1987-05-01), Taub
patent: 4833638 (1989-05-01), Vollaro
patent: 4920486 (1990-04-01), Nielsen
patent: 5179661 (1993-01-01), Copeland, III et al.

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