Selective precharge circuit for read-only-memory

Details Selective precharge circuit for read-only-memory Selective precharge circuit for read-only-memory

1979-07-27

1982-03-02

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

365104, 365203, 365230, H03K 19096, G11C 802

Patent

active

043180140

ABSTRACT:
A read-only-memory circuit is disclosed which includes a plurality of column conductors and circuitry for selecting one of the plurality of column conductors in response to an input address. The selection circuitry couples each of the column conductors to a common node which is coupled to a precharge circuit such that only the selected column conductor is precharged. The precharged circuit includes first and second diode-connected IGFET devices coupled in series such that the first IGFET device is a standard enhancement mode transistor which includes an implanted channel while the second IGFET device is a natural transistor which does not include an implanted channel.

REFERENCES:
patent: 3611437 (1971-10-01), Varadi et al.
patent: 3613055 (1971-10-01), Varadi et al.
patent: 3740731 (1973-06-01), Ohwada et al.
patent: 4021781 (1977-05-01), Caudel et al.
patent: 4094008 (1978-06-01), Lockwood et al.
patent: 4139907 (1979-02-01), Blahut et al.
patent: 4145759 (1979-03-01), Remedi
patent: 4183093 (1980-01-01), Kawagoe
patent: 4185321 (1980-01-01), Iwahashi et al.

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