Selective power distribution circuit for an integrated circuit

Details Selective power distribution circuit for an integrated circuit Selective power distribution circuit for an integrated circuit

2000-06-19

2002-03-12

Nelms, David (Department: 2818)

Static information storage and retrieval

Powering

C365S189070, C365S195000, C365S200000, C365S201000

Reexamination Certificate

active

06356498

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to a power distribution system for an integrated circuit.
BACKGROUND OF THE INVENTION
As the device geometries of integrated circuits continue to decrease with improvements in manufacturing processes, greater numbers of circuits can be fabricated on a single integrated circuit die. There is also an increased probability that at least some of these circuits will be defective in some way. It has become standard practice in the design of Dynamic Random Access Memory (DRAM) devices to provide redundant memory elements that can be used to replace defective memory elements and thereby increase device yields. Redundant elements can only be used to repair certain types of defects by replacing a row, column or an array of devices. Depending on the particular defect repaired, the device may exhibit undesirable characteristics such as increased standby current, speed degradation, reduction in operating temperature range, or reduction in supply voltage range as a result of the defect being present on the die. Certain other types of defects cannot be repaired effectively through redundancy techniques alone. Defects such as power to ground shorts in a portion of the array can prevent the device from operating even to the extent required to locate the defect in a test environment. Memory devices with limited known defects have been sold as “partials”, “audio RAMs” or “off spec devices” provided that the defects do not prohibitively degrade the performance of the functional portions of the memory. The value of a partially functional device decreases dramatically as the performance of the device deviates from that of the standard fully functional device. The desire to make use of devices with limited defects, and the problems associated with the performance of these devices due to the defects are well known in the industry.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an integrated circuit which can be modified after fabrication using a selective power distribution system to isolate portions of the integrated circuit and maximize production yield.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. An integrated circuit is described which includes separate sub-section voltage generators that can be selectively controlled to modify the integrated circuit after fabrication.
In particular, the present invention describes a memory device comprising a plurality of memory arrays, a plurality of voltage generators, each voltage generator coupled to one of the plurality of memory arrays for supplying a voltage to the one of the plurality of memory arrays, and control circuitry for selectively disabling the plurality of voltage generators to non-volatilely interrupt the voltage supplied to the plurality of memory arrays and reduce the operational capacity of the memory device.
In a second embodiment, a memory device is described which comprises a plurality of memory arrays, a plurality of voltage generators, each voltage generator coupled to one of the plurality of memory arrays for supplying a voltage to the one of the plurality of memory arrays. The plurality of voltage generators comprise an amplifier circuit having a disable input for receiving a disable signal. The memory further comprises control circuitry for providing the disable signal to selectively disable the plurality of voltage generators to non-volatilely interrupt the voltage supplied to the plurality of memory arrays and reduce the operational capacity of the memory device, and a data map circuit for coupling memory device data outputs to the plurality of memory arrays so that a consistent memory device pin out is maintained when operational capacity of the memory device is changed.
In another embodiment, power distribution circuitry is described for use in an integrated circuit comprising a plurality of voltage generator circuits. Each voltage generator circuit coupled to one of a plurality of separate integrated circuit sub-sections provides the sub-section with a voltage supply. The plurality of voltage generator circuits includes a disable input for receiving a disable signal. The power distribution circuitry includes a control circuit coupled to the plurality of voltage generator circuits for providing the disable signal, the disable signal being either volatile for temporarily interrupting the voltage supply to an integrated circuit sub-section, or non-volatile for permanently interrupting the voltage supply to an integrated circuit sub-section.
In yet another embodiment, a method of producing a reduced capacity memory device is described as comprising the steps of manufacturing a memory die with multiple arrays of memory elements each coupled to one of multiple voltage supply generators to achieve functionality, testing the memory die, and permanently disabling at least one of the voltage supply generators from the multiple arrays of memory elements.


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