Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Treating electrolytic or nonelectrolytic coating after it is...
Reexamination Certificate
2000-05-09
2002-04-09
Gorgos, Kathryn (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Treating electrolytic or nonelectrolytic coating after it is...
C205S221000, C205S223000, C438S687000
Reexamination Certificate
active
06368484
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to fabrication and packaging processes for semiconductor devices, and more particularly to electroplating processes for fabricating metal structures generally greater than 3 &mgr;m thick, especially thick lines of copper.
BACKGROUND OF THE INVENTION
Electroplating is a widely used process in semiconductor manufacturing. Unfortunately, electroplating is a cumbersome process when it is desired to fabricate large structures such as metal lines on the order of 5 &mgr;m, for RF applications or for inductors capable of high-Q oscillations.
A conventional electroplating process for a thick metal line is shown in
FIGS. 1A-1C
. A substrate (alternatively, an interlevel dielectric such as SiO
2
)
10
has a feature
11
formed therein. A liner/adhesion promoter
12
for the plated line is deposited on the surface, including the sidewalls and bottom of feature
11
. In the case of copper electroplating, layer
12
is typically a combination of tantalum nitride (in contact with the substrate
10
) and tantalum; layer
12
serves as a copper diffusion barrier while promoting adhesion to the substrate.
As shown in
FIG. 1A
, a seed layer
13
for the metal to be plated is deposited over the entire surface. Plating is then performed on the entire surface, until feature
11
is filled in with plated metal
14
(see FIG.
1
B). To ensure that the entire feature is filled in, plating continues until an excess of plated metal appears in areas
15
outside feature
11
. This excess (sometimes called overburden) must then be removed with a planarization process such as chemical-mechanical polishing (CMP), to finally yield a thick metal line as shown in FIG.
1
C. The amount of necessary overburden depends on the size of the metal line being fabricated. If a variety of feature sizes are being plated, plating must continue until the largest feature is filled in, while smaller features are substantially overplated. This process is costly in terms of both time and materials; most of the plated metal
14
must be removed, and the planarization process is time-consuming.
Accordingly, there is a need for an improved electroplating process in which overburden is reduced or eliminated, so that the subsequent planarization process is shortened or avoided.
SUMMARY OF THE INVENTION
The present invention addresses the above-described need by providing a method of electroplating a metal structure in a feature formed in a substrate, such that no electroplating occurs in areas outside the feature where plating is desired. This is done by depositing a seed layer of the metal on the top surface of the substrate and the bottom and sidewalls of the feature, and then selectively removing the seed layer from at least the top surface. The seed layer is thus reduced to a portion in the feature (on at least the bottom thereof). The metal is then electroplated using that portion of the seed layer, so that the metal fills the feature.
The substrate may have a liner covering the top surface and the bottom and sidewalls of the feature, so that the seed layer is deposited on the liner. After electroplating, the liner and the metal are planarized so that the liner is removed from the top surface of the substrate and the top surface of the plated metal is made substantially planar with the top surface of the substrate. The planarization is preferably performed using chemical-mechanical polishing (CMP).
The present invention may be advantageously practiced when electroplating copper, with a liner including tantalum and tantalum nitride.
According to one aspect of the invention, the seed layer is deposited on the liner (including on the top surface of the substrate and on the sidewalls and bottom of the feature), and then selectively removed from the liner on the top surface. This selective removal is performed by CMP of the seed layer. The liner on the top surface is thus exposed, and the seed layer is reduced to a portion in the feature on the sidewalls and on the bottom thereof. The metal is then electroplated using that portion of the seed layer, so that metal fills the feature; the removal of the seed layer from the top surface causes electroplating not to occur on the top surface, but only in the feature where plating is desired. The plated metal is then planarized (preferably by CMP) so that a top surface of the metal is planar with the liner exposed on the top surface. Finally, the plated metal and the liner on the top surface are planarized so that the liner is removed from the top surface of the substrate, and the top surface of the metal is substantially planar with the top surface of the substrate.
According to another aspect of the invention, the seed layer is selectively removed by using a self-aligned masking layer. After the liner is deposited on the substrate (including the top surface, and the sidewalls and bottom of the feature where plating is desired) and the seed layer is deposited on the liner, a masking layer is deposited on the seed layer. This masking layer (preferably an organic material, deposited by a spin coating process) is then selectively removed from the top surface and the upper portion of the sidewalls; the remaining portion of the masking layer masks the seed layer at the bottom of the feature and the lower portion of the sidewalls. The exposed portion of the seed layer is then removed. The remaining portion of the masking layer is then removed, so that the remaining portion of the seed layer is exposed. The metal is then electroplated using this portion of the seed layer, so that the metal fills the feature. The plating process may be controlled so that a top surface of the metal is substantially planar with the top surface of the substrate. The removal of the seed layer from the top surface causes electroplating not to occur on the top surface. Finally, the liner on the top surface is planarized (preferably by CMP) to remove the liner therefrom. Since the plating process is performed when the only remaining portion of the seed layer is inside the feature on the bottom and lower sidewalls thereof, the plated metal may be confined to the interior of the feature. Accordingly, the use of a self-aligned masking layer permits control of the plating process so that only one planarization is required.
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patent: 3385773 (1968-05-01), Frantzen
patent: 3464855 (1969-09-01), Shaheen et al.
patent: 5198389 (1993-03-01), van der Putten et al.
patent: 5240879 (1993-08-01), De Bruin
patent: 5256274 (1993-10-01), Poris
patent: 5308796 (1994-05-01), Feldman et al.
patent: 5549808 (1996-08-01), Farooq et al.
patent: 5933758 (1999-08-01), Jain
patent: 6071814 (2000-06-01), Jang
Electroless Plating for Low-Cost High-Leverage Wiring, IBM Technical Disclosure Bulletin, vol. 32 No. 3A, Aug. 1989.
Locke Peter S.
Petrarca Kevin S.
Rockwell David M.
Subbanna Seshadri
Volant Richard P.
Abate Joseph P.
Anderson Jay H.
Gorgos Kathryn
International Business Machines - Corporation
Tran Thao
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