Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-03-27
2007-03-27
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C257SE21525
Reexamination Certificate
active
10966114
ABSTRACT:
A method for manufacturing a semiconductor device includes, (a) mounting a plurality of first semiconductor chips in a manner not to overlap with one another on a substrate having a plurality of wiring patterns formed thereon, and electrically connecting each of the first semiconductor chips to any one of the wiring patterns, (b) conducting an electrical examination on a plurality of mounted bodies each including one of the first semiconductor chips and any one of the wiring patterns electrically connected to each other, (c) stacking a second semiconductor chip on the first semiconductor chip of any one of the mounted bodies that pass the electrical examination, excluding any of the mounted bodies that fail the electrical examination and thereafter, (d) cutting the substrate so as to divide the wiring patterns. The electrical examination in step (b) includes a test on each of the wiring patterns, a test on each of the first semiconductor chips, and a test on an electrical connection state between each of the first semiconductor chips and a corresponding one of the wiring patterns, and wherein the electrical examination is a success when passing all of the tests, and the electrical examination is a failure when failing at least one of the tests.
REFERENCES:
patent: 5222014 (1993-06-01), Lin
patent: 6589801 (2003-07-01), Yoon et al.
patent: 2003/0224542 (2003-12-01), Liu
patent: 01-098253 (1989-04-01), None
patent: 06-013541 (1994-01-01), None
patent: 08-204123 (1996-08-01), None
patent: 08-213548 (1996-08-01), None
patent: 10-084076 (1998-03-01), None
patent: 2001-257310 (2001-09-01), None
patent: 2002-299384 (2002-10-01), None
patent: 2002-329813 (2002-11-01), None
patent: 2003-501805 (2003-01-01), None
patent: 2004-253667 (2004-09-01), None
patent: 2004-273938 (2004-09-01), None
patent: 00/74136 (2000-12-01), None
Japanese Publication No. 06-013541 corresponds to U.S. Patent No. 5,222,014.
Coleman W. David
Hogan & Hartson LLP
Seiko Epson Corporation
LandOfFree
Selective packaging of tested semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective packaging of tested semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective packaging of tested semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3731490