Selective over-ranging in folding and averaging integrated...

Details Selective over-ranging in folding and averaging integrated... Selective over-ranging in folding and averaging integrated...

2000-11-01

2002-04-09

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06369742

ABSTRACT:

This invention is related, in general, to signal conversion and signal processing and the use of integrated circuits to perform these functions. More specifically, this invention provides a circuit and method using averaging, folding and interpolating for converting analog data to digital data.
It is common that converters provide conversion of analog signals to binary bits, providing N-bit accuracy. Typically this requires 2
N
pre-amps and comparators, making the analog-to-digital integrated circuit complex. Integrated circuit implementations of analog-to-digital converters face the design trade off of increased resolution versus minimizing the cost and complexity overhead.
One method of reducing the number of comparators is known as folding. Signal folding involves combining the differential outputs of several pre-amplifiers at a common comparator. In three times folding, three differential pre-amplifiers drive each comparator. Classical folding begins with the generation of a folded version of an input signal and then quantizing that folded signal. However, this simplified approach results in distortion at the bends, i.e., locations where the folded signal has zero slope and then reverses slope. Each folded signal is slightly offset from the adjacent folded signals such that the bend in the fold is not used. The family of folded signals is interpolated to effectively increase the quantity of input signals and enhance the accuracy of the converter.
Another limitation of the prior art is cell mismatch. Cell mismatch occurs when successive pairs of differential pre-amplifiers have amplification differences. Individual mismatches between pre-amplifiers result in errors known as Differential Non-Linearity (DNL). The accumulation of DNL mismatch error is known as Integral Non-Linearity (INL).
A process referred to as averaging purports to solve the errors associated with DNL and INL. Averaging takes into account a group of folded signals above and below the zero crossing. This technique requires the incorporation of current sources and impedance strips, i.e., resistor strips, coupled to the outputs of the pre-amplifier cells. This architecture intends to “average out” cell mismatches by adding folds in the pre-amplifier circuits, an inefficient and costly solution.
By now it should be appreciated that a cost-effective solution to the problem of averaging differential and integral non-linearity at the upper and lower extremes of the input signal range is needed.


REFERENCES:
patent: 5157397 (1992-10-01), Vernon
patent: 5471210 (1995-11-01), Wingender et al.
patent: 5835047 (1998-11-01), Vorenkamp et al.
patent: 5835048 (1998-11-01), Bult

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