Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
1999-09-09
2001-02-20
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S204000, C365S189070, C365S202000
Reexamination Certificate
active
06191969
ABSTRACT:
BACKGROUND
1. Field of Invention
This invention relates generally to semiconductor memories and specifically to content addressable memories.
2. Description of Related Art
A CAM includes an array of memory cells arranged in a matrix of rows and columns. Each memory cell stores a single bit of digital information, i.e., either logic zero or logic one. The bits stored within a row of memory cells constitute a CAM word. During compare operations, a comparand word is received at appropriate input terminals of the CAM and then compared with all the CAM words. For each CAM word that matches the comparand word, a corresponding match line signal is asserted to indicate a match condition. When there is a match condition, the index or address of the matching CAM word is read from the CAM. Associative information stored in, for instance, an associated RAM, may also be provided.
FIG. 1
shows a typical CAM row
1
as having n CAM cells
10
(
1
)-
10
(n) each coupled to an associated match line ML. A pull-up transistor
12
, coupled between a supply voltage V
DD
and match line ML, has a gate tied to ground potential, and therefore remains in a conductive state. Prior to each compare operation between an n-bit comparand word and an n-bit CAM word stored in CAM cells
10
(
1
)-
10
(n), match line ML is pre-charged to supply voltage V
DD
via pull-up transistor
12
. The n-bits of the comparand word are compared with corresponding bits of the CAM word in respective CAM cells
10
(
1
)-
10
(n). If all bits of the comparand word match corresponding bits of the CAM word, the match line ML remains charged to indicate a match condition. Conversely, if one of the comparand bits does not match the corresponding CAM bit, the CAM cell
10
storing that CAM bit discharges match line ML toward ground potential to indicate a mismatch condition.
As described above, the match lines in a CAM array are typically pre-charged to the supply voltage V
DD
for each and every compare operation. Thus, for each mismatch condition, an associated match line ML is first charged toward V
DD
and then discharged toward ground potential. Current flow associated with this charging and discharging results in undesirable power consumption. Further, as the number of CAM cells in each row of a CAM array increases, capacitive loading on the match lines increases accordingly. As loading on the match lines increases, the current required to charge the match lines toward the supply voltage increases. Accordingly, as CAM words are widened, for example, to accommodate longer Internet addresses, power consumption resulting from charging the match lines during compare operations may significantly increase. It is therefore desirable to reduce power consumption during compare operations.
SUMMARY
A method and apparatus are disclosed that may reduce power consumption associated with pre-charging match lines in a content addressable memory (CAM) during compare operations. In accordance with one embodiment of the present invention, each row of a CAM array is partitioned into a plurality of row segments, with each row segment having a number of CAM cells coupled to a corresponding match line segment. Each CAM cell is coupled to ground potential through a corresponding discharge circuit. The discharge circuits corresponding to CAM cells in each row segment are responsive to match conditions in a preceding row segment. The discharge circuits in the first row segment are responsive to a disable signal.
During compare operations between a comparand word and CAM words stored in corresponding rows of the CAM array, all match line segments in the corresponding rows are pre-charged toward a supply voltage to enable evaluation of match conditions therein. For each row segment, if there is a match between corresponding bits of the comparand and CAM words, the CAM cells in the segment maintain the corresponding match line segment in the charged state to indicate the match condition. In response thereto, the discharge circuits corresponding to a subsequent row segment turn on to allow the subsequent match line segment to reflect match conditions in the subsequent row segment. On the other hand, if there is a mismatch condition in the row segment, the CAM cells and discharge circuits therein discharge the match line segment toward ground potential. In response to this mismatch condition, the discharge circuits in the subsequent row segment(s) turn off to prevent discharging of the subsequent match line segment(s), thereby preventing match conditions in the subsequent row segment(s) from affecting a match signal for the row. Here, the mismatch condition of the preceding row segment may be propagated along the row to indicate a mismatch condition for the row without discharging subsequent match line segments. When the subsequent match line segments remain in the charged state, they may not need to be pre-charged for the next compare operation. As a result, power consumption associated with match line pre-charging may be reduced in subsequent compare operations.
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Net Logic Microsystems, Inc.
Nguyen Viet Q.
Paradice III William L.
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