Selective low power clocking apparatus and method

Details Selective low power clocking apparatus and method Selective low power clocking apparatus and method

1995-12-20

1997-10-14

Voeltz, Emanuel T.

Boots, shoes, and leggings

364707, 395750, G06F 132

Patent

active

056778490

ABSTRACT:
A selective low power clocking apparatus and method is used to reduce power consumption by an electronic system or integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits or functional blocks. Each sub-circuit or functional block is configured to operate under control of a clock signal and further includes an apparatus for holding or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, the clock signal to that sub-circuit is disabled. The arbiter circuit continuously monitors the system bus. Upon detecting that the external system needs to transmit or receive signals from the electronic system or integrated circuit, the arbiter re-enables the clock signal to the sub-circuits which are required for the transmission or reception.

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