Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-02-27
2003-09-09
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S255000
Reexamination Certificate
active
06617222
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor manufacture and, more particularly, to a method for inhibiting hemispherical grain silicon (HSG) growth on selected locations of a container capacitor storage plate.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor devices which comprise memory elements, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and some microprocessors, container capacitors are commonly formed. Container capacitors are well known to allow an increased stored charge over planar capacitors by increasing the surface area on which the charge may be stored. To further increase the surface area on which the charge may be stored, polysilicon storage nodes are commonly converted to hemispherical silicon grain (HSG) polysilicon. This material has a roughened surface compared with non-HSG polysilicon and, therefore, an increased surface area on which a charge may be stored.
FIGS. 1-8
depict a conventional method for forming a container capacitor from HSG polysilicon.
FIG. 1
depicts a semiconductor wafer substrate assembly
10
comprising a semiconductor wafer
12
having a plurality of doped areas
14
which allow proper operation of a plurality of transistors
16
. Each transistor comprises gate oxide
18
, a doped polysilicon control gate
20
, silicide
22
such as tungsten silicide to increase conductivity of the control gate, and a capping layer
24
of tetraethyl orthosilicate (TEOS) oxide. Silicon nitride spacers
26
insulate the control gate
20
and silicide
22
from polysilicon pads
28
to which the container capacitors will be electrically coupled. Further depicted in
FIG. 1
is shallow trench isolation (STI, field oxide)
30
which reduces unwanted electrical interaction between adjacent control gates, and a thick layer of deposited oxide
32
such as borophosphosilicate glass (BPSG). A patterned photoresist layer
34
defines the location of the container capacitors to be formed. The
FIG. 1
structure may further include one or more bit (digit) lines under the TEOS layer or various other structural elements or differences which, for simplicity of explanation, have not been depicted.
The
FIG. 1
structure is subjected to an anisotropic etch which removes the exposed portions of the BPSG layer to form a patterned BPSG layer which provides a base dielectric having a recess for the container capacitor. During this etch the polysilicon pads
28
and possibly a portion of TEOS capping layer
24
are exposed as depicted in FIG.
2
. The remaining photoresist layer is stripped and any polymer (not depicted) which forms during the etch is removed according to means known in the art to provide the
FIG. 3
structure.
As depicted in
FIG. 4
, a blanket polysilicon layer
40
is formed conformal with the deposited oxide layer, and will provide a container capacitor storage node for the completed capacitor. A thick blanket filler material
42
, such as photoresist, is formed to fill the containers provided by polysilicon
40
. The
FIG. 4
structure is then subjected to a planarizing process, such as a chemical planarization, a mechanical planarization, or a chemical mechanical planarization (CMP) step. This process removes horizontal portions of the photoresist
42
, the polysilicon
40
, and usually a portion of the BPSG
32
to result in the
FIG. 5
structure.
Next, the BPSG
32
is partially etched with an etch selective to polysilicon (i.e. an etch which minimally etches or, preferably, doesn't etch polysilicon) to result in the structure of FIG.
6
. At this point in the process the polysilicon storage nodes
40
are only minimally supported. The bottom plates
40
in the
FIG. 6
structure each comprise a first region
60
which defines a recess, and a second region
62
which defines an opening to the recess, with the first and second regions being continuous, each with the other. In other words, the bottom plate
40
of
FIG. 6
defines a receptacle having a rim
62
which defines an opening to the interior of the receptacle. The regions
60
,
62
form vertically-oriented sides of the bottom plate, and the sides are electrically-coupled by a horizontally-oriented bottom
64
.
After etching the BPSG, a process is performed which converts the smooth polysilicon to HSG polysilicon storage plates
70
as depicted in FIG.
7
. Various processes for converting the smooth polysilicon to HSG polysilicon are known in the art.
After performing the conversion of the smooth polysilicon to HSG polysilicon, a cell dielectric layer
80
, for example a layer of high-quality cell nitride, a polysilicon container capacitor top plate
82
, and a planar oxide layer such as BPSG
84
are formed according to means known in the art to result in the
FIG. 8
structure. Subsequently, wafer processing continues according to means known in the art.
One problem which may result during the process described above is flaking of the HSG polysilicon from the storage node
70
as depicted in FIG.
9
. These loose portions
90
are conductive and thus, when they break off and contact two adjacent conductive structures, can short the structures together and result in a malfunctioning or nonfunctioning device. Typically, the greatest number of such defect occurs proximate the top of the storage plates. This may occur as these ends are not protected by adjacent structures. This may also occur because, as wafer processing continues, the tops are the most likely portion of the storage plate to be contacted during a CMP or other step, and also incur the highest stresses.
Another problem which may occur with the process described above results from the very close lateral spacing between adjacent storage plates. As a design goal of semiconductor engineers is to form as many storage capacitors per unit area as possible, and there are typically several million storage capacitors on each memory chip, even a small decrease in spacing between features can allow for the formation of many more features in the same area. Thus the capacitors are formed as close together as wafer processing will allow. As the roughened polysilicon grains grow, grains from two adjacent plates can form a bridge
92
between the two plates and thus short them together to result in a malfunctioning device.
A method used to form roughened polysilicor container capacitor storage plates which reduces or eliminates the problems described above, and a structure resulting therefrom, would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method which, among other advantages, reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting during the formation of hemispherical silicon grain (HSG) polysilicon container capacitor storage plates. In accordance with one embodiment of the invention a container capacitor layer is formed, for example from polysilicon, which comprises a first region defining a recess and a second region defining an opening to the recess. The first and second regions are formed having a smooth texture. Next, an inhibitor layer is formed over the second region of the container capacitor layer while a majority of the first region of the container capacitor layer remains free from the inhibitor layer. With the inhibitor layer extending over the second region of the container capacitor layer, at least a portion of the first region is converted to have a second texture which is rougher than the first texture, for example a conversion to HSG polysilicon. Subsequent to this conversion, the second region still has the first, smoother texture. Finally, the conversion inhibitor layer may be removed and is therefore a sacrificial layer, or more preferably it may be left in by place, and wafer processing continues to complete the semiconductor device.
Using this process, the highest defect source for HSG flaking is removed, which results in decreased device defects. Various embodiments of the invention are described.
Advantages will become apparent to tho
Martin Kevin D.
Micro)n Technology, Inc.
Nguyen Tuan H.
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