Boots – shoes – and leggings
Patent
1987-10-19
1988-10-18
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 944, G06F 932
Patent
active
047791888
ABSTRACT:
The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.
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Curlee, III Thomas O.
Gum Peter H.
Hough Roger E.
Tallman Peter H.
Goldman Bernard M.
Harkcom Gary V.
International Business Machines - Corporation
Lynt Christopher H.
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