Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For high frequency device
Reexamination Certificate
2000-04-04
2002-09-17
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For high frequency device
C257S506000, C257S508000, C257S522000, C257S778000, C257S664000, C257S787000, C438S421000, C333S247000
Reexamination Certificate
active
06452267
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates generally to integrated circuit devices. In particular, the invention relates to high frequency integrated circuit devices having a reduced degree of signal degradation.
2. Background of the Invention
An integrated circuit device typically includes a substrate coupled with a silicon chip. A plurality of electrical conductors provide electrical communication between the substrate and the silicon chip. An underfill is positioned between the substrate and the silicon chip in order to provide structural integrity to the integrated circuit device.
During operation of such an integrated circuit device, electrical signals carried by the electrical conductors often exhibit varying degrees of degradation as evidenced by an increase in the bit error rate. Higher frequency signals exhibit a larger degree of degradation than lower frequency signals. This degradation often affects the ability of the integrated circuit device to process high frequency signals. As a result, there is a need for an integrated circuit device having a reduced degree of high frequency signal degradation.
SUMMARY OF THE INVENTION
The invention relates to an integrated circuit device. The device includes a substrate and a silicon chip having first electronics and second electronics, wherein the second electronics operate at higher frequencies than the first electronics. Electrical conductors provide electrical communication between the package substrate and the silicon chip. A first portion of the electrical conductors are in communication with the first electronics and a second portion of the electrical conductors are in communication with the second electronics. A first medium is positioned adjacent to the first portion of electrical conductors and a second medium is positioned adjacent to the second portion of electrical conductors. The second medium is different from the first medium.
Another embodiment of the device includes electrical conductors providing electrical communication between a substrate and a silicon chip. A solid first medium is positioned adjacent to a first portion of electrical conductors and a second medium is positioned adjacent to a second portion of electrical conductors. The second medium is different from the solid first medium.
The invention also relates to a method of forming an integrated circuit device. The method includes providing an integrated circuit device having electrical conductors providing electrical communication between a substrate and a silicon chip; and forming a solid first medium between the silicon chip and the substrate. The solid first medium is positioned adjacent to a first portion of electrical conductors and is not positioned adjacent to a second portion of electrical conductors.
In another embodiment, the method includes providing an integrated circuit device having electrical conductors providing electrical communication between a substrate and a silicon chip. The silicon chip includes first electronics and second electronics which operate at higher frequencies than the first electronics. A first portion of electrical conductors are in communication with the first electronics and a second portion of electrical conductors are in communication with the second electronics. The method also includes forming a first medium between the silicon chip and the substrate such that the first medium is positioned adjacent to a first portion of electrical conductors and is not positioned adjacent to a second portion of electrical conductors. The first medium can be a solid or a fluid.
REFERENCES:
patent: 5567982 (1996-10-01), Bartelink
patent: 5604017 (1997-02-01), Frankosky
patent: 5694300 (1997-12-01), Mattie et al.
patent: 5768109 (1998-06-01), Gullick et al.
patent: 5840382 (1998-11-01), Nashide et al.
patent: 5889449 (1999-03-01), Fiedziuszko
patent: 5982032 (1999-11-01), Ishikawa et al.
patent: 6025261 (2000-02-01), Farrar et al.
patent: 6141847 (2000-11-01), Mizuno et al.
patent: 6184121 (2001-02-01), Buchwalter et al.
patent: 6356173 (2002-03-01), Nagata et al.
LeClair Timothy L.
Nettles Mary Jo
Applied Micro Circuits Corporation
Gray Cary Ware & Freidenrich
Parekh Nitin
Thomas Tom
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