Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-05-03
2003-02-18
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S720000, C438S723000, C438S724000
Reexamination Certificate
active
06521539
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming patterned layers within microelectronic fabrications. More particularly, the present invention relates to selective etch methods for forming patterned layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
In the course of forming patterned microelectronic layers within microelectronic fabrications, including but not limited to patterned microelectronic conductor layers, patterned microelectronic semiconductor layers and patterned microelectronic dielectric layers within microelectronic fabrications, it is often desirable to selectively etch a first microelectronic layer in the presence of a second microelectronic layer, where the first microelectronic layer and the second microelectronic layer are formed of either equivalent microelectronic materials or sufficiently similar microelectronic materials such that the first microelectronic layer would not otherwise etch selectively with respect to the second microelectronic layer.
An example, by no means limiting, where it is desired to selectively etch within the context of the above limitations a first microelectronic layer in the presence of a second microelectronic layer is illustrated within the schematic cross-sectional diagram of FIG.
1
.
Shown in
FIG. 1
is a substrate
10
upon which there is formed a second intermediate patterned microelectronic layer
12
, which in turn has formed thereupon a third upper patterned microelectronic layer
14
. Within
FIG. 1
, the substrate
10
comprises a first lower microelectronic layer which is formed of a first material either equivalent to a second material from which is formed the third upper patterned microelectronic layer
14
or sufficiently similar such that the substrate
10
and the third upper patterned microelectronic layer
14
are otherwise etchable in the same etchant. Within the context of
FIG. 1
, a problem towards which the present invention is directed is stripping from the second intermediate patterned microelectronic layer
12
the third upper patterned microelectronic layer
14
while not etching the substrate
10
.
It is thus towards the goal of forming within microelectronic fabrications microelectronic structures which result from selectively etching a third upper patterned microelectronic layer in the presence of a first lower microelectronic layer, where the third upper patterned microelectronic layer is separated from the first lower microelectronic layer by a second intermediate patterned microelectronic layer, and where the third upper patterned microelectronic layer is not otherwise selectively etchable within the presence of the first lower microelectronic layer.
Various etch methods have been disclosed in -the art of microelectronic fabrication for forming patterned layers with desirable properties within microelectronic fabrications.
For example, Tsai et al., in U.S. Pat. No. 5,753,418, discloses a method for forming within a microelectronic fabrication a patterned layer of aperture width dimension as narrow as about 0.30 microns while employing near ultra-violet (NUV) (i.e. 365 nm) photoexposure radiation. The method employs forming interposed between: (1) a patterned photoresist layer which is patterned employing the near ultra-violet (NUV) photoexposure radiation which provides within the patterned photoresist layer an aperture width dimension typically as narrow as about only 0.35 microns; and (2) a blanket target layer to be patterned while employing the patterned photoresist layer, a blanket focusing layer. The blanket focusing layer is formed of an organic anti-reflective coating (ARC) material which is susceptible to providing a reproducible positive taper of a patterned focusing layer when forming the patterned focusing layer from the blanket focusing layer while employing a plasma etch method which employs an etchant gas composition comprising carbon tetrafluoride and argon. The patterned focusing layer may then be employed as an etch mask for forming a patterned target layer from the blanket target layer.
In addition, Linliu et al., in U.S. Pat. No. 5,773,199, discloses a method for forming within a microelectronic fabrication a patterned microelectronic fabrication structure, such as a gate electrode within a field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, with a linewidth at least as narrow as about 0.25 microns while employing near ultra-violet (NUV) (i.e. 365 nm) photoexposure radiation. Similarly with Tsai et al., as cited above, the method employs forming interposed between: (1) a patterned photoresist layer which is patterned employing the near ultra-violet (NUV) photoexposure radiation; and (2) a blanket target layer which is desired to be patterned while employing the patterned photoresist layer, a blanket focusing layer. However, in contrast with that which is disclosed by Tsai et al., the blanket focusing layer is formed from an organic anti-reflective coating (ARC) material which is susceptible to a reproducible negative etch bias when patterned to form a patterned focusing layer while employing a plasma etch method employing an etchant gas composition comprising trifluoromethane, carbon tetrafluoride, oxygen and argon. The patterned focusing layer may then be employed as an etch mask for forming a patterned target layer from the blanket target layer.
Finally, McKee, in U.S. Pat. No. 5,804,088, also discloses a method for forming within a microelectronic fabrication a patterned layer of linewidth dimension less than about 0.30 microns while employing near ultra-violet (NUV) (i.e. 365 nm) photoexposure radiation. Similarly with the foregoing disclosures, the method employs an intermediate layer formed interposed between: (1) a target layer to be patterned with the linewidth dimension of less than about 0.30 microns; and (2) a patterned photoresist formed employing the near ultra-violet (NUV) photoexposure radiation, where the patterned photoresist layer is further isotropically etched while simultaneously forming a patterned intermediate layer of linewidth less than the patterned photoresist layer, and where the patterned intermediate layer is then employed as an etch mask for forming a patterned target layer from the target layer.
Desirable in the art of microelectronic fabrication are methods for forming within microelectronic fabrications microelectronic structures which result from selectively etching a third upper patterned microelectronic layer in the presence of a first lower microelectronic layer, where the third upper patterned microelectronic layer is separated from the first lower microelectronic layer by a second intermediate patterned microelectronic layer, and where the third upper patterned microelectronic layer is not otherwise selectively etchable within the presence of the first lower microelectronic layer.
It is towards the foregoing object that the present invention is both generally and more specifically directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for selectively etching within a microelectronic fabrication a third upper patterned microelectronic layer with respect to a first lower microelectronic layer within a multi-layer microelectronic stack layer within the microelectronic fabrication, where the third upper patterned microelectronic layer is separated from the first lower microelectronic layer by a second intermediate patterned microelectronic layer within the multi-layer microelectronic stack layer.
A second object of the present invention is tor provide a method in accord with the first object of the present invention, where the third upper patterned microelectronic layer within the multi-layer microelectronic stack layer is not otherwise selectively etchable with
Dai Xue Chun
Yap Chiew Wah
Zhou Mei Sheng
Brown Charlotte A.
Chartered Semiconductor Manufacturing Ltd.
Kunemund Robert
Pike Rosemary L. S.
Saile George O.
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