Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-10-11
2002-02-19
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030
Reexamination Certificate
active
06349062
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a method of erasing multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomena of hot electron injection to trap charge within a trapping dielectric material within the gate.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM.
An example of a single transistor Oxide-Nitrogen-Oxide (ONO) EEPROM device is disclosed in the technical article entitled “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programmed by hot electron injection and the injected charges are stored in the oxide-nitride-oxide (ONO) layer of the device. This article teaches programming and reading in the forward direction. Thus, a wider charge trapping region is required to achieve a sufficiently large difference in threshold voltages between programming and reading. This, however, makes it much more difficult to erase the device.
Erasure of EEPROM devices in general is disclosed in U.S. Pat. Nos. 5,077,691; 5,561,620; 5,598,369; 5,617,357; 5,708,588 and for ONO EEPROM devices is disclosed in both U.S. Pat. No. 5,768,192 and PCT patent application publication WO 99/07000, the contents of each reference identified above are hereby incorporated herein by reference. In those disclosed devices, a cell is erased by applying a negative voltage to the gate or a zero bias on the gate in conjunction with a large, positive bias on the drain over a plurality of cycles.
As shown in
FIG. 1
, a well known technique for erasing an array of non-volatile memory cells
41
in a flash memory device
102
is to apply a large positive voltage to the drains
34
along each of the bit lines
104
while simultaneously grounding or applying a small negative voltage to the gates
42
along each of the word lines
106
. This results in all of the memory cells
41
being erased simultaneously. It is believed that erasure of the memory cells
41
is accomplished by “hot” or “warm” holes, generated through band-to-band tunneling, being injected into the nitride trapping layer of the memory cells
41
resulting in the neutralization or compensation for trapped electrons in the nitride trapping layer. This simultaneous erasure of multiple memory cells is disadvantageous in that individual cells cannot be erased.
SUMMARY OF THE INVENTION
One aspect of the invention regards a method of selectively erasing a bit of an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that include a first non-volatile two bit memory cell that is connected in series with a second non-volatile memory cell. The method includes erasing a first bit of the first non-volatile two bit memory cell while not erasing a second bit of the first non-volatile memory cell.
The above aspect of the present invention provides the advantage of allowing individual cells of an array of non-volatile memory cells.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.
REFERENCES:
patent: 5471423 (1995-11-01), Iwasa
Advanced Micro Devices , Inc.
Phan Trong
Tran M.
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