Selective erase method for flash memory

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185290, C365S185300, C365S185180

Reexamination Certificate

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10960542

ABSTRACT:
Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.

REFERENCES:
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patent: 5831905 (1998-11-01), Hirano
patent: 5995418 (1999-11-01), Chen et al.
patent: 6314027 (2001-11-01), Choi
patent: 6836435 (2004-12-01), Li
patent: 09-320282 (1997-12-01), None
patent: 2001-283595 (2001-10-01), None
patent: 000036391 (2000-07-01), None
patent: 000038225 (2000-07-01), None
patent: 20010098374 (2001-11-01), None
Notice to Submit a Response for Korean Patent Apllication No. 10-2004-0056902 mailed on Mar. 7, 2006.

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