Fishing – trapping – and vermin destroying
Patent
1991-02-28
1991-12-17
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 90, 437228, 437 67, 437941, 437 69, 148DIG26, 148DIG50, 148DIG97, H01L 2120
Patent
active
050735160
ABSTRACT:
This is a method of fabricating a high-performance semiconductor device. The method comprises: forming a first insulating structure, preferably a layer of silicon nitride (e.g. region 24 in FIG. 2) on a layer of thermally grown oxide (e.g. region 22), on a substrate (e.g. region 20), preferably silicon; patterning and anisotropically etching the first insulating structure to expose a portion of the substrate and sidewalls of the first insulating structure; forming a second insulating structure, preferably a layer of oxide (e.g. region 28 in FIG. 3) on a layer of nitride (the bottom second insulating layer is preferably an etch-stop layer with respect to the removal of the top second insulating layer) (e.g. region 26 in FIG. 3), on the patterned first insulating structure, along the sidewalls of the first insulating structure, and on the exposed semiconductor substrate; anisotropically removing portions of the second insulating structure leaving a sidewall region of the second insulating structure (e.g. regions 30 and 32 in FIG. 4) along the sidewall of the first insulating structure and a region of the second insulating structure on a portion of the exposed substrate, and exposing a portion of the exposed substrate; forming a region of semiconducting material (e.g. regions 36 and 34, respectively, in FIG. 5), preferably a selectively grown semiconducting layer (preferably in-situ doped epitaxial silicon), encompassed by the second insulating structure and the exposed region of the substrate; sequentially and selectively etching the second insulating sidewall region to substantially expose the sidewalls of the selectively grown semiconducting region and top of the semiconducting region; and forming a third insulating layer (e.g. region 40 in FIG. 8 and region b 46 in FIG. 11), preferably a thermally grown oxide layer or a low-temperature plasma oxidation layer, on the exposed semiconducting region and on the exposed sidewalls of the semiconducting region.
REFERENCES:
patent: 4758531 (1988-07-01), Beyer et al.
"Silicon Selective Epitaxial Growth and Electrical Properties of Epi/Sidewall Interfaces" Ishitani et al., Japanese Jour. of Appl. Physics, Part 1. May, 1989, pp. 841-848.
"Silicon Selective Epitaxial Growth at 800.degree. C. Using SiH.sub.4 /H.sub.2 Assisted by H.sub.2 /Ar Plasma Sputter", Yew et al., Appl. Phys, Lett. 55(10), Sep., 1989, pp. 1014-1016.
"Low-Temperature Silicon Selective Deposition and Epitaxy on Silicon Using the Thermal . . . " Appl. Physics Lett. 54(11), Mar. 1989, Murota et al., pp. 1007-1009.
"Low-Temperature Selective Epitaxial Growth of Silicon at Atmospheric Pressure" Sedgwick et al. Appl. Phys. Lett 54(26), Jun., 1989, pp. 2689-2691.
SEG Materials Status 1988, "Third Annual Innovations in Epitaxial Technology for Advanced Device Structures", Seminar, John O. Borland.
"Advanced DRAM Structures incorporating Selective Epitaxy", Third Annual Innovations in Epitaxial Technology for Advanced Device Structures Seminar, Gary Bronner.
"Selective Epitaxial Growth for CMOS Isolation", Stivers et al., Components Research Intel Corporation, Santa Clara, CA.
Braden Stanton C.
Comfort James T.
Dang Trung
Hearn Brian E.
Sharp Melvin
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