Selective electroless plating of vias in VLSI devices

Details Selective electroless plating of vias in VLSI devices Selective electroless plating of vias in VLSI devices

1986-03-03

1987-09-08

Smith, John D.

Fishing, trapping, and vermin destroying

427305, 437236, C23C 1834

Patent

active

046923497

ABSTRACT:
Selective electroless plating of cobalt or nickel is utilized to form conductive plugs in high-aspect-ratio vias in VLSI devices. Particularly good results are obtained when an active or catalytic film is formed on the via bottoms to serve as a plating base.

REFERENCES:
patent: 4182781 (1980-01-01), Hooper
patent: 4297393 (1981-10-01), Denning
patent: 4419390 (1983-12-01), Feldstein
patent: 4542074 (1985-09-01), Sirinyan
Coleman et al., "The Pd.sub.2 Si-(Pd)-Ni-Solder Plated Metallization for Silicon Solar Cells" Conference, 13th IEEE Photovoltacic-Specialists Conference, Washington, D.C. (Jun. 5-8, 1978), pp. 597-602.

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