Selective dynamic RAM address generator with provision for autom

Details Selective dynamic RAM address generator with provision for autom Selective dynamic RAM address generator with provision for autom

1990-06-06

1992-07-14

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sequential

36518912, 365222, 365236, G11C 804

Patent

active

051309238

ABSTRACT:
An improved address generator for generating address values for refresh, read and write functions in a dynamic random access memory (RAM). Whether a refresh, write column, write row, read column or read row RAM addressing operation is to be performed is first determined. A shift register for storing and shifting at least one of the address values for each of the RAM addressing operations has its output connected to the address port of the RAM. A bit is selectively added, in response to the determination of which RAM addressing operation is to be performed, to the output of the shift register and the added value is submitted to the input of the shift register. A controller causes a data shift in the shift register at least once each time a bit is added to the value of the output of the shift register.

REFERENCES:
patent: 4006468 (1977-02-01), Webster
patent: 4727481 (1988-02-01), Aquille et al.

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