Selective differential low-noise amplifier

Details Selective differential low-noise amplifier Selective differential low-noise amplifier

2008-05-27

2008-05-27

Nguyen, Patricia (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S302000

Reexamination Certificate

active

11519789

ABSTRACT:
A selective differential low-noise amplifier includes a pair of transistors, each transistor of the pair being connected by its source to a current source and by its gate and/or its source to a differential voltage source, a coupling circuit between the gate of each transistor and the source of the other transistor of the pair, and, for each transistor of the pair, at least one series resonance and parallel resonance resonator connected in series between the source and/or the gate of the transistor and the differential voltage source.

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Galal et al, “40Gb/s Amplifier and ESD Protection Circuit in 0.18 μm CMOS Technology”, Solid-State Circuits Conference, Session 26, 2004 IEEE, Feb. 15, 2004, pp. 480-489.
Runge et al, On-chip matched 5.2 and 5.8 GHz differential LNAs Fabricated using 0.35 μm CMOS technology, Electronics Letters, vol. 35, No. 22, Oct. 28, 1999, pp. 1899-1900.

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