Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-08-31
2003-02-18
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S396000, C438S695000, C438S964000
Reexamination Certificate
active
06521507
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor field effect transistors, and in particular to selective depostion on polysilicon surfaces.
BACKGROUND OF THE INVENTION
Dynamic random access memories (DRAMs) are a widely used form of semiconductor memory. DRAMs are composed of a memory cell array and peripheral circuitry. Each memory cell array is formed of a plurality of memory cells for storing information. Typical memory cells are formed with a transistor for accessing a capacitor that stores charge. Of primary concern is maximizing the storage capacitance of each memory cell capacitor. This need is particularly acute in light of the demand for high density DRAMs, without increasing the chip area required to form the cell and, preferably, allowing a decrease in the chip area per cell.
One way to achieve greater capacitance per cell is to increase the surface area of the capacitor electrodes without increasing the respective cell area. As can be seen from the following equation, capacitance, C, is roughly determined by the thickness of the capacitor insulator (t
ox
), the surface area of the capacitor electrodes (A), and the dielectric constant of the capacitor insulator (∈).
C=
(
∈·A
)/
t
ox
Increasing the surface area of the capacitor electrodes by forming the storage capacitor in a container like shape is well known in the art. To further increase circuit density in DRAMs stacked capacitors are used. These capacitors are actually stacked on top of the substrate, which may or may not include access devices. Two or more layers of a conductive material called electrodes formed of polysilicon or poly are deposited over the substrate with dielectric layers sandwiched between each electrode.
U.S. Pat. No. 5,340,765 to Dennison et al., herein incorporated by reference, describes a method for further increasing the surface area of a bottom electrode of such capacitors by forming the electrode surfaces with hemispherical grained polysilicon (HSG). First, a portion of an oxide layer covering access circuitry on a semiconductor wafer is removed to form a container. A bottom electrode is then formed by growing an amorphous silicon layer. The amorphous silicon layer is then seeded by flowing silane or disilane at elevated temperatures.
After seeding, the wafer is annealed to form HSG on both sides of the doped silicon layer. Formation of a dielectric layer and top capacitor plate complete the capacitor formation.
While the above method creates a roughened surface on the capacitor electrode plate to increase capacitance per unit area, it can lead to undesired deposits forming on oxide, BPSG or other insulator between structures where silicon is desired to be deposited. Such conductive deposits are referred to as stringers which are caused by residual poly film deposited on oxide surfaces that short nearby storage cells or other structures where it is desired to form the poly film. Further steps, such as etches are then required to eliminate such shorting.
There is a need to form poly films in a selective manner. There is a need to form selective poly films in a manner which reduces the need for further processing steps to remove undesired residual poly film. There is yet a further need to form selective poly films without forming shorts between structures on which the film is desired. There is a further need to form such poly films only where formation of HSG is desired. With the rapid decrease in device size, coupled with the demand for increased performance, a new, efficient technique must be found to provide an increase in the capacitance per unit area in DRAM memory cells without causing shorts between cells.
SUMMARY OF THE INVENTION
A chlorine containing gas mixture is flowed during seeding of polysilicon layers to enhance formation of films in a selective manner. The chlorine containing gas enhances selectivity of film formation such that film forms on the polysilicon layers while formation of the film on adjacent insulative layers is inhibited.
In one embodiment of the invention, polysilicon layers of a capacitive storage cell are seeded with hydride gases such as silane, disilane or trisilane while a chlorine containing gas, such as HCl is introduced. The seeding is performed at a temperature of approximately 500 to 800 degrees Celsius. Pressures of up to near atmosphere may be used while still maintaining high selectivity. The seeding is followed by an anneal at a temperature of approximately 500 to 800 degrees Celsius. No retooling from prior HSG formation processes is required, and the higher selectivity provides the ability to modify other process parameters to acheive other goals while still maintaining adequate selectivity.
In a further embodiment, polysilicon structures supported by a substrate are separated by adjacent insulative layers such as oxides or BPSG. The structures are selectively seeded by silane or disilane in the presence of a chlorine containing gas to selectively form a polysilicon film. The use of the chlorine containing gas greatly inhibits the formation of the film between the structures, greatly reducing the chance of a short between the structures.
In yet a further embodiment, a DRAM device comprises multiple stacked capacitive cells having bottom electrodes with selectively seeded HSG. The use of chlorine during seeding of the bottom electrodes provides an increase in the capacitance per unit area in the DRAM memory cells without causing shorts between cells.
In a further variation, polysilicon structures supported by a substrate are separated by adjacent insulative layers such as oxides or BPSG, and the structures are selectively seeded in the presence of an etchant which selectively etches the insulative layers. This inhibits the formation of polysilicon nucleation sites on the insulative layers, resulting in greatly reduced formation of shorts between the structures.
REFERENCES:
patent: 4579609 (1986-04-01), Reif et al.
patent: 5130885 (1992-07-01), Fazan et al.
patent: 5340765 (1994-08-01), Dennison et al.
patent: 5405801 (1995-04-01), Han et al.
patent: 5407534 (1995-04-01), Thakur
patent: 5411912 (1995-05-01), Sakamoto
patent: 5418180 (1995-05-01), Brown
patent: 5444013 (1995-08-01), Akram et al.
patent: 5573968 (1996-11-01), Park
patent: 5634974 (1997-06-01), Weimer et al.
patent: 5658381 (1997-08-01), Thakur et al.
patent: 5759262 (1998-06-01), Weimer et al.
patent: 5770500 (1998-06-01), Batra et al.
patent: 5830793 (1998-11-01), Schuegraf et al.
patent: 5882979 (1999-03-01), Ping et al.
patent: APPL. 61-5068 (1986-01-01), None
Wolf et al, “Silicon Processing For The VLSI Era, vol. 1: Process Technoloty.” Lattice Press, Sunset Beach, CA: 1986, pp. 520,559-561.*
Wolf, S., et al., “Silicon Processing for the VLSI Era”,vol. 1 Process Technology, Lattice Press, Sunset Beach, Ca, 156-156, 178, 222, (1986).
Wolf, S., et al., “Silicon Processing for the VLSI Era”,vol. 1: Process Technology, Lattice Press, Sunset Beach, Ca, 520, 559-561, (1986).
Pan James
Thakur Randhir P. S.
Chaudhuri Olik
Huynh Yennhu B.
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