Selective code generation optimization for an advanced...

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C717S144000, C717S151000, C717S160000

Reexamination Certificate

active

08087010

ABSTRACT:
Mechanisms for selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization.

REFERENCES:
patent: 4802091 (1989-01-01), Cocke et al.
patent: 5287510 (1994-02-01), Hall et al.
patent: 5293631 (1994-03-01), Rau et al.
patent: 5475842 (1995-12-01), Gilbert et al.
patent: 5535393 (1996-07-01), Reeve et al.
patent: 5808915 (1998-09-01), Troyanovsky
patent: 5812852 (1998-09-01), Poulsen et al.
patent: 5822593 (1998-10-01), Lamping et al.
patent: 5881291 (1999-03-01), Piazza
patent: 5946484 (1999-08-01), Brandes
patent: 5999737 (1999-12-01), Srivastava
patent: 6026240 (2000-02-01), Subramanian
patent: 6038398 (2000-03-01), Schooler
patent: 6058266 (2000-05-01), Megiddo et al.
patent: 6064819 (2000-05-01), Franssen et al.
patent: 6078745 (2000-06-01), De Greef et al.
patent: 6106575 (2000-08-01), Hardwick
patent: 6226790 (2001-05-01), Wolf et al.
patent: 6247173 (2001-06-01), Subrahmanyam
patent: 6253373 (2001-06-01), Peri
patent: 6282706 (2001-08-01), Chauvel et al.
patent: 6286135 (2001-09-01), Santhanam
patent: 6339840 (2002-01-01), Kothari et al.
patent: 6357041 (2002-03-01), Pingali et al.
patent: 6367071 (2002-04-01), Cao et al.
patent: 6427234 (2002-07-01), Chambers et al.
patent: 6507947 (2003-01-01), Schreiber et al.
patent: 6588009 (2003-07-01), Guffens et al.
patent: 6651246 (2003-11-01), Archambault et al.
patent: 6654952 (2003-11-01), Nair et al.
patent: 6745384 (2004-06-01), Biggerstaff
patent: 6772415 (2004-08-01), Danckaert et al.
patent: 6948160 (2005-09-01), Click et al.
patent: 6952821 (2005-10-01), Schreiber
patent: 7000213 (2006-02-01), Banerjee et al.
patent: 7107199 (2006-09-01), Schreiber et al.
patent: 7162716 (2007-01-01), Glanville et al.
patent: 7254679 (2007-08-01), Richter et al.
patent: 7484079 (2009-01-01), Gupta et al.
patent: 2001/0032332 (2001-10-01), Ward et al.
patent: 2003/0200538 (2003-10-01), Ebeling et al.
patent: 2004/0003386 (2004-01-01), Tal et al.
patent: 2004/0019883 (2004-01-01), Banerjee et al.
patent: 2004/0068718 (2004-04-01), Cronquist et al.
patent: 2005/0273770 (2005-12-01), Eichenberger et al.
patent: 2005/0273772 (2005-12-01), Matsakis et al.
patent: 2007/0174829 (2007-07-01), Brockmeyer et al.
patent: 2008/0263530 (2008-10-01), Rahavan et al.
patent: 2009/0083722 (2009-03-01), Eichenberger et al.
patent: 2009/0083724 (2009-03-01), Eichenberger et al.
patent: 2009/0307673 (2009-12-01), Eichenberger et al.
Title: Run-Time parallelization and scheduling of loops, author: Saltz et al, source: IEEE, dated: May 1991.
Title: Theory and algorithms for the generation and validation of speculative loop optimizations, Ying Hu et al, dated: Sep. 23, 2004, source: IEEE.
U.S. Appl. No. 11/861,449, 1 page.
U.S. Appl. No. 11/861,503, 1 page.
U.S. Appl. No. 11/861,512, 2 pages.
Devos et al., “Hardware Generation from the Polyhedral Model”, http://escher.elis.ugent.be/publ/Edocs/DOC/P106—165.pdf, 4 pages.
Vasilache et al., “Polyhedral Code Generation in the Real World”, INRIA, 2006, available at http://hal.inria.fr/inria-00001106/en/, 15 pages.
Bastoul et al., “Putting Polyhedral Loop Transformations to Work”, Workshop on Languages and Compilers for Parallel Computing (LCPC'03), LNCS, Springer-Verlag, College Station, Texas, Oct. 2003, pp. 23-30.
Bastoul, Cedric, “Code Generation in the Polyhedral Model is Easier Than You Think”, PACT'13 IEEE International Conference on Parallel Architecture and Compilation Techniques, Juan-les-Pins, Sep. 2004, pp. 7-16.
Girbal et al., “Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies”, International Journal of Parallel Programming, vol. 34, No. 3, Jun. 2006, pp. 261-317.
Quillere et al., “Generation of Efficient Nested Loops from Polyhedra”, International Journal of Parallel Programming, Oct. 2000, 30 pages.
Vasilache, Nicolas, “Scalable Program Optimization Techniques in the Polyhedral Model”, Thesis for Doctor of Philosophy, To Be Defended on Sep. 28, 2007, Universite de Paris-SUD, U.F.R. Scientifique d'Orsay, Inria Futurs, 216 pages.
U.S. Appl. No. 11/861,449, filed Sep. 26, 2007, Eichenberger et al.
U.S. Appl. No. 11/861,503, filed Sep. 26, 2007, Eichenberger et al.
U.S. Appl. No. 11/861,512, filed Sep. 26, 2007, Eichenberger et al.
Interview Summary mailed Apr. 20, 2011 for U.S. Appl. No. 11/861,512, 3 pages.
Notice of Allowance mailed Jun. 23, 2011 for U.S. Appl. No. 11/861,512, 10 pages.
Response to Office Action filed with the USPTO on Jun. 29, 2011 for U.S. Appl. No. 11/861,503, 26 pages.
Kandemir, Mahmut et al., “Improving Memory Energy Using Access Pattern Classification”, Nov. 2001, pp. 201-206, <http://delivery.acm.org/10.1145/610000/603136/p201-kandemir.pdf>.
Quillere, Fabien et al., “Optimizing Memory Usage in the Polyhedral Model”, Sep. 2000, pp. 773-815, <http://delivery.acm.org/10.1145/370000/365152/p773-quillere.pdf>.
Notice of Allowance mailed Jul. 22, 2011 for U.S. Appl. No. 11/861,449, 20 pages.
Notice of Allowance mailed Aug. 26, 2011 for U.S. Appl. No. 11/861,503, 15 pages.
Gottlob, Georg et al., “Normalization and Optimization of Schemema Mappings”, The VLDB Journal, 2011, pp. 277-302.
Hazelwood, Kim et al., “Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems”, IEEE CGO, 2001, pp. 1-11.
Jeffords, Ralph D. et al., “Using Invariants to Optimize Formal Specifications Before Code Synthesis”, IEEE, 2004, pp. 73-82.
Lin, Joey Y. et al., “Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization”, ACM DAC, 2006, pp. 472-477.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Selective code generation optimization for an advanced... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selective code generation optimization for an advanced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective code generation optimization for an advanced... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4312127

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.