Selective carry boundary

Details Selective carry boundary Selective carry boundary

1998-06-19

2001-06-19

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S630000

Reexamination Certificate

active

06249799

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to microprocessor technology, and more specifically, the present invention relates the use of an arithmetic logic unit (ALU) to perform a variety to multiplication formats.
BACKGROUND OF THE INVENTION
The multiplication of two values is a common operation performed in arithmetic logic units. A conventional multiplier (e.g., a 16×16 multiplier) receives a 16-bit multiplicand and a 16-bit multiplier and generates a 32-bit product using a Wallace tree.
The multiplier requires input values of a fixed bit length of 16 bits each. In order to multiply values having other bit length (e.g., a 4×4 multiplication), the input values must be bit extended with additional bits having no additional information. For example, if a 4×4 operation is to be performed, the 4-bit input values must be extended to 16 bits before multiplication. The additional 12 bits of each input have no useful information resulting in the 32-bit product having 24 bits of useless information.
Furthermore, the current multiplier is limited in that it only performs multiplication in series, one multiplication per operation cycle.
Therefore, what is desired is a circuit and method which 1) increase the input bit size format flexibility of the multiplier thereby reducing input value bit extension, and 2) allow for several multiplications to be performed in parallel using a single multiplier.
SUMMARY OF THE INVENTION
An adder tree includes one partial product generator for generating a bit of a first partial product. The adder tree includes another partial product generator for generating a bit of a second partial product, the two bits having equal weight.
An adder is coupled to receive the two bits of the first and second partial product generators. The adder generates a carry bit on a carry terminal, the carry bit having a weight one digit greater than the weight of the two bits.
A logic unit has an instruction terminal, an input terminal, and an output terminal. The input terminal of the logic unit is coupled to receive the carry bit from the carry terminal at the input terminal of the logic unit. The logic unit provides the carry bit on its output terminal in response to a first instruction on the instruction terminal. The logic unit provides a value independent of the value on the input terminal (e.g., a binary 0 regardless of the input value) in response to a second signal on the instruction terminal.
The above circuit and method provide for a carry boundary which can be selectively activated to block carries generated on one side of the carry boundary from being transmitted to the other side of the carry boundary.


REFERENCES:
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4825401 (1989-04-01), Ikumi
patent: 5189636 (1993-02-01), Patti et al.
patent: 5432728 (1995-07-01), Curtet
patent: 5742538 (1998-04-01), Guttag et al.
patent: 5880985 (1999-03-01), Makineni et al.

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