Selective calling receiver with multiple clock frequencies for r

Details Selective calling receiver with multiple clock frequencies for r Selective calling receiver with multiple clock frequencies for r

1992-03-30

1993-08-03

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

3403111, H04B 700

Patent

active

052333450

ABSTRACT:
A selective calling receiver includes a decoder having a reference clock oscillator and a CPU having a CPU operating clock oscillator. The decoder includes a timing control circuit for generating a timing signal in synchronism with a synchronizing signal contained in a POCSAG signal and a BCH error correcting circuit for extracting a message code from the POCSAG signal. If the CPU is supplied with a message code from the decoder when no timing signal is inputted from the decoder, the CPU stores the message code in RAM in the CPU or a buffer memory area of external RAM connected to the CPU. In this case, the CPU operates with a first clock signal generated by the reference clock oscillator. When the CPU is supplied with the timing signal from the decoder, the CPU reads the message code from the RAM or the buffer memory area and processes the message code with a second clock signal generated by the CPU operating clock oscillator and the second clock signal has a frequency higher than the frequency of the first clock signal.

REFERENCES:
patent: 4618860 (1986-10-01), Mori
patent: 4704608 (1987-11-01), Sato et al.
patent: 4758834 (1988-06-01), Sato et al.
Standard Message Formats for Digital Radio Paging, Post Office Code Standardization Advisory Group (POCSAG), Autumn, 1980.

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