Selective call receiver having CMOS power-on reset circuit

Details Selective call receiver having CMOS power-on reset circuit Selective call receiver having CMOS power-on reset circuit

1992-12-03

1994-09-20

Urban, Edward F.

Telecommunications

Transmitter and receiver at separate stations

455343, 3072723, 3072965, 307363, H04Q 302, H03K 1730

Patent

active

053496957

ABSTRACT:
A selective call receiver (100) operates to recover an information signal and is capable of receiving a battery supplying a first voltage (203) that is multiplied to generate a second voltage (212). The selective call receiver (100) includes [comprises] a processor (106) that extracts message information contained within the recovered information signal for presentation and a power-on reset circuit (112) that generates a power-on reset signal having [comprising] first and second portions corresponding with a processor reset and a processor execute state, respectively. The power-on reset signal changes from the processor reset to the processor execute state when the second voltage (212) exceeds a sum of a PMOS threshold voltage and a NMOS threshold voltage, thereby completing a power-on reset of the processor (106).

REFERENCES:
patent: 4001609 (1977-01-01), Sickert
patent: 4697097 (1987-09-01), Rusznyak
patent: 4902910 (1990-02-01), Hsieh
patent: 4983857 (1991-01-01), Steele
patent: 5032825 (1991-07-01), Kuznicki

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