Selective C4 connection in IC packaging

Details Selective C4 connection in IC packaging Selective C4 connection in IC packaging

2002-10-01

2003-11-18

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S779000, C257S780000, C257S782000, C438S108000, C438S613000, C228S180220

Reexamination Certificate

active

06650016

ABSTRACT:

TECHNICAL FIELD
The field of the invention is that of packaging integrated circuits, in particular the connection technology referred to as “flip-chip” or C4.
BACKGROUND OF THE INVENTION
In the process of fabricating substrates for connecting sets of integrated circuits, (ICs) manufacturers sometimes have occasion to make selected contacts with the solder bump connections on the bottom of an integrated circuit. For example, there may be a set of similar products that have different connections to a standard chip, so that the kth bump on the chip is used with some packages and not used with others.
In the past, as shown in
FIG. 3
in cross section, a chip
10
having a ball grid array of solder bump contacts
30
(referred to as “flip chip” technology or as C4 technology) would all be soldered to metal contact pads
110
in a corresponding contact array on the top surface
135
of the substrate. In that case, the chip would have to be designed and manufactured with only those contacts that were used. U.S. Pat. No. 6,229,219 illustrates different chips with irregular sets of contacts on the bottom. All of the contacts on each chip are bonded to corresponding contacts on the package. The package accommodates two different chips by having empty locations on the chip—i.e. a chip has an empty location at the kth slot on that chip so there is no bond formed between the contact at the kth location and the empty slot on the chip.
Alternatively, a chip would be bonded to a contact on the package, but contacts that were not used would be “floating”, i.e. not connected to further layers of the package. This meant that there was potential for such contacts pads
110
to short out to other contacts. Additionally, the metal on the substrate represented capacitance that might affect the operation of the chip. Removing the contact on the bottom of the chip would cost money for different masks in forming the chip contacts. Removing the contact after the chip is formed would require extra handling, with the possibility of damaging the chip. Removing the contact pad
110
at that location was a possibility, but there was a chance that the solder bump
30
would flow to short out an adjacent contact, or a via that had been fabricated below the contact pad
110
, even with the presence of solder mask
130
, a conventional dielectric layer that is deposited and patterned photolithographically. The solder mask in this prior art view is shown as separating the solder bumps
30
and the corresponding metal pads
110
that the solder bumps make contact with, as is conventional.
SUMMARY OF THE INVENTION
The invention relates to a structure of isolating unused solder bumps on the bottom of an IC by patterning the metal interconnect on the top surface of the substrate, together with the solder mask, to isolate the unused solder bumps.
A feature of the invention is changing the shape of a metal interconnect passing under an unused chip contact to form a depression in the dielectric solder mask to lower the height of the solder mask at the selected location.
Another feature of the invention is patterning the solder mask to place a layer of dielectric between a contact on a chip and a corresponding contact on the package.


REFERENCES:
patent: 5400950 (1995-03-01), Myers et al.
patent: 5677575 (1997-10-01), Maeta et al.
patent: 5748450 (1998-05-01), Kim et al.
patent: 5773882 (1998-06-01), Iwasaki
patent: 5872393 (1999-02-01), Sakai et al.
patent: 6229219 (2001-05-01), Bhagath et al.
patent: 6380002 (2002-04-01), Hsu et al.
patent: 01185952 (1989-07-01), None
patent: 07273243 (1995-10-01), None

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