Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-02-08
2005-02-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S350000
Reexamination Certificate
active
06852638
ABSTRACT:
A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer (6) of silicon-germanium on a substrate (1) of monocrystalline silicon or on a substrate at least comprising a surface layer of monocrystalline silicon, depositing at least a dielectric layer (7) on the silicon-germanium layer (6) and patterning the resultant structure (8), whereafter the dielectric layer (7) and the silicon-germanium layer (6) are etched away within a predetermined region (9). Preferably, the silicon-germanium layer (6) is amorphous, whereby the dielectric layer (7) is deposited on the amorphous silicon-germanium layer (6) in such a manner to prevent crystallization of the amorphous layer. After etching the structure may be heat-treated such that the amorphous layer crystallizes. The method is preferably applicable for etching an emitter window in the manufacture of a bipolar transistor having a self-registered base-emitter structure.
REFERENCES:
patent: 4988632 (1991-01-01), Pfiester
patent: 5213989 (1993-05-01), Fitch et al.
patent: 5217564 (1993-06-01), Bozler et al.
patent: 5266504 (1993-11-01), Blouse et al.
patent: 5431777 (1995-07-01), Austin et al.
patent: 5484740 (1996-01-01), Cho
patent: 5502330 (1996-03-01), Johnson et al.
patent: 5592017 (1997-01-01), Johnson
patent: 5600174 (1997-02-01), Reay et al.
patent: 5616508 (1997-04-01), Johnson
patent: 5817580 (1998-10-01), Violette
patent: 6077752 (2000-06-01), Norström
patent: 6255183 (2001-07-01), Schmitz et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 0103726-6 (2003-07-01), None
patent: WO 9719465 (1997-05-01), None
B. Tillack et al; “Monitoring of deposition and dry etching of Si/SiGe multiple stacks”; J. Vac. Sci. Technol. B14(I)9, pp. 1184-1198, Jan./Feb. 1996.
Tsu-Jae King et al.; “A Polycrystalline-Si1-xGex-GATE CMOS Technology”; Center for Integrated Systems, Stanford University, Stanford, CA, Apr. 1990.
E. Josse, et al; “High performance 0.1 μpMOSFETs with optimized poily-Si and poly-SiGe gates”.
J.A. Babcok et al.; “Precision electrical Trimming of Very Low TCR Poly-SiGe Resistors” IEEE Electron Device Letters. vol. 21, No. 6, Jun., 2000.
S. Wolf et al.; “for the VLSI Era”; vol. 1—Process Technology; p. 565-567.
D. L. Harame; et al.; “Si/SiGe Epitaxial-Base Transistors-Part II: Process Integration and Analog Applications” IEEE Transactions on Electron Devices, vol. 42, No. 3, Mar. 1995.
T.H. Ning, et al.; “Self-Aligned NPN Bipolar Transistors”; International Electron Devices Meeting; Washington, D.C., Dec. 1980.
Johansson Ted
Norström Hans
Baker & Botts L.L.P.
Infineon - Technologies AG
Luk Olivia
Niebling John F.
LandOfFree
Selective base etching does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective base etching, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective base etching will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3465994