Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2003-02-25
2004-04-06
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S119000, C341S121000
Reexamination Certificate
active
06717536
ABSTRACT:
TECHNICAL FIELD
The present invention relates to analog-to-digital (A/D) converters, and in particular to background calibration of such converters.
BACKGROUND
The performance of any A/D converter is limited by non-ideal effects associated with its various building blocks. The influence of several such effects can be addressed by digital calibration, e.g. as described in [1], where a set of digital calibration coefficients are used to correct the estimated analog circuit errors. A problem is that the calibration coefficients are most accurate when the circuit is operated under exactly the same conditions as when the coefficients were estimated. If, for example, the temperature, the supply voltage, or a bias current is changed, a new set of coefficients may be required for optimal error correction.
Usually, a technique called background calibration [2] is used to continuously calibrate the A/D converter during normal operation. However, the background calibration process disturbs the normal signal flow through the A/D converter, and therefore causes an error in the output. There are techniques to reduce the magnitude of such errors, e.g. by interpolation as described in [3]. Nevertheless, the signal interrupts caused by background calibration of the A/D converter lead to an increased bit-error rate in, for example, digital communication systems. It would be desirable, both from a signal quality and power efficiency point of view, to avoid background calibration of the A/D converter whenever possible.
SUMMARY
An object of the present invention is to provide background calibration techniques for A/D converters at a lower bit-error rate penalty than in the prior art.
This object is achieved in accordance with the attached claims.
Briefly, the present invention is based on the insight that background calibration is normally not necessary during times when operating conditions are stable. By using on-chip or off-chip sensors for critical operating parameters, such as temperature and supply voltage, it becomes possible to suppress unnecessary background calibration under stable operating conditions, thus lowering the bit-error rate in steady-state.
REFERENCES:
patent: 3703001 (1972-11-01), Hibbs, Jr.
patent: 4133036 (1979-01-01), Watson
patent: 5101206 (1992-03-01), Riedel
patent: 5121119 (1992-06-01), Higuchi et al.
patent: 5450336 (1995-09-01), Rubsamen et al.
patent: 6069576 (2000-05-01), Gwin
patent: 6255976 (2001-07-01), Watanabe et al.
patent: 6414612 (2002-07-01), Quesenberry
patent: 6473012 (2002-10-01), Hellberg et al.
patent: 6496125 (2002-12-01), Jonsson et al.
patent: 0 981 204 (2000-02-01), None
International Search Report mailed Dec. 10, 2001 in corresponding PCT application No. PCT/SE01/01803.
International Preliminary Examination Report completed Jul. 16, 2002 in corresponding PCT application No. PCT/SE01/01803.
Erdo{haeck over (g)}an et al, WA 18.1 -A 12b Digital-Background-Calibrated Algorithmic ADC with -90dB THD:, 1999, IEEE International Solid-State Circuits Conference.
Kwak et al, “A 15-b, 5-Msample/s Low-Spurious CMOS ADC”, 1999, IEEE Journal of Solid-State Circuits, vol. 32, No. 12, Dec. 1997, pp. 1866-1875.
Razavi, “Design of Analog CMOS Integrated Circuits” Preview Edition, McGraw-Hill Higher Education.
Ming et al, “MP 2.5 -An 8b 80Msample/s Pipelined ADC with Background Calibration”, 2000, ISSCC 2000/Session 2/Nyquist-Rate Data Converters/Paper MP 2.5, IEEE International Solid-State Circuits Conference.
Ingino et al, “A Continuously Calibrated 12-b, 10-MS/s, 3.3-V A/D Converter”, IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 1920-1931.
Moon et al, “Background Digital Calibration Techniques for Pipelined ADC's”, IEEE Transactions on Circuits and Systems -II; Analog and Digital Signal Processing, vol. 44, No. 2, Feb. 1997, pp. 102-109.
Mai Lam T.
Nixon & Vanderhye P.C.
Telefonaktiebolaget LM Ericsson (publ)
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