Selective back side wet etch

Details Selective back side wet etch Selective back side wet etch

1999-08-26

2002-08-06

Goudreau, George (Department: 1763)

Etching a substrate: processes

Nongaseous phase etching of substrate

With measuring, testing, or inspecting

C216S099000, C438S007000, C438S008000, C438S016000, C438S745000, C438S750000, C438S753000

Reexamination Certificate

active

06428718

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving selective wet etching.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or “flip-chip” packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is “flipped” over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is bulk silicon.
The positioning of the circuit side near the package provides many of the advantages of the flip chip. However, in some instances orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
For flip-chips and other dies requiring or benefiting from back side access, techniques have been developed to access the circuit even though the integrated circuit (IC) is buried under the bulk silicon. For example, near-infrared (nIR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of nIR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using nIR microscopy. For a die that is 725 microns thick, at least 625 microns of silicon is removed before nIR microscopy can be used.
Thinning the die for analysis of an IC requiring or benefiting from back side access is usually accomplished by first globally thinning, wherein the silicon is thinned across the entire die surface. The silicon is globally thinned to allow viewing of the active circuit from the back side of the die using nIR microscopy. Mechanical polishing and chemical-mechanical polishing are two example methods for global thinning. Using nIR microscopy, an area is identified for accessing a particular area of the circuit.
Another method used for etching semiconductors is wet etching. In a typical wet etch process, a wet chemical solution is introduced to a surface of a semiconductor device. Reactants in the solution diffuse to and react with the surface. The reaction can include the adsorption of the reactants into the surface, and subsequent desorption of reaction byproducts after the reaction takes place. The reaction products diffuse from the surface and are removed. For example, a typical reaction during wet etching of silicon involves the formation of an oxide layer on the silicon surface via the introduction of reactants to the surface which results in oxidation. The oxide layer is subsequently dissolved, effectively etching the surface. This process is commonly known as an oxidation-reduction (redox) reaction.
Wet etching is often used to selectively etch a substrate on which desired features of an integrated circuit have been masked, such as with an applied photoresist. The photoresist can be applied to a silicon surface in a desired pattern. A wet etch process is then applied, and the surface is etched to match the pattern. Although it has experienced widespread use for front side etching of silicon in semiconductor devices, wet etching has been generally inapplicable to back side etching.
SUMMARY OF THE INVENTION
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to an example embodiment of the present invention, a semiconductor device having a back side and a circuit side opposite the back side is analyzed. The semiconductor device includes bulk silicon in the back side and epitaxial silicon. A wet etch solution comprising tetramethylammonium hydroxide (TMAH) is directed at the back side. Using the wet etch solution, the back side is selectively etched and an exposed region is formed. The etching is selective to the bulk silicon. When the etching process encounters the epitaxial silicon, the etch rate slows and is used as an endpoint indicator of the selective etching process. Once the etching process is stopped, the circuitry is accessed via the exposed region.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.


REFERENCES:
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patent: 5071510 (1991-12-01), Findler et al.
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Thong, J.T.L., Choi, W.K., Chong, C.W.,TMAH Etching of Silicon and the Interaction of Etching Parameters, 1997, pp. 1-7.
Material Satefy Data Sheet—Tetramethylammonium hydroxide, 25% (Aqueous solution) pp. 1-5.
Malberti, P., Ciappa, M., Scacco, P.,A New Back-Etch for Silicon Devices, 1997, pp. 257-261.

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