Selective asperity definition technique suitable for use in fabr

Details Selective asperity definition technique suitable for use in fabr Selective asperity definition technique suitable for use in fabr

1988-12-12

1991-04-16

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 52, 437195, 437193, 437228, 437233, H01L 21265, H01L 2170

Patent

active

050082124

ABSTRACT:
In a semiconductor fabrication technique, a first patterned layer (16) of nonmonocrystalline semiconductor material is created on a substructure (10, 12, 14). An insulating layer (22) is thermally grown along the patterned layer in such a way that the upper edge of the remainder (16A) of the patterned layer forms an asperity (24). A blanket layer 26, preferably consisting of nonmonocrystalline semiconductor material, is formed over the insulating layer. Using an etchant that attacks the blanket and patterned layers more than the insulating layer, a selective etch is performed to remove a section of the blanket layer. The etch is continued past the blanket layer to remove the underlying portion of the insulating layer located along the asperity and then, importantly, to remove the so exposed part of the asperity. The remainder (26A) of the blanket overlies the remainder ( (24A) of the asperity. The technique is particularly useful in manufacturing a floating-gate FET for an electrically erasable programmable device. The remainder of the asperity facilitates tunneling during erasure.

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patent: 4853895 (1989-08-01), Mitchel et al.

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