Selective area double epitaxial process for fabricating silicon-

Details Selective area double epitaxial process for fabricating silicon- Selective area double epitaxial process for fabricating silicon-

1986-07-30

1987-04-21

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148175, 148187, 148DIG77, 357 91, H01L 21263, H01L 21225

Patent

active

046593926

ABSTRACT:
A process is disclosed for preparing selectively doped and recrystallized silicon-on-insulator semiconductor wafers, and wafers prepared thereby, wherein successive amorphizing and annealing sequences are utilized to optimize the defect structure and doping of multiple regions or islands of the silicon on an insulator substrate. Prior to fabrication of the active devices, the various silicon islands are given customized ion implantation treatments to amorphize a silicon near-interface layer under differing sets of implantation conditions. The entire wafer is then annealed to achieve downward epitaxial recrystallization of the amorphized near-interface layers in all of the amorphized islands, growing on the near-surface crystalline layer of the silicon remote from the interface. The near-surface layers of the islands are then amorphized and annealed to achieve upward epitaxial recrystallization of the layers on the underlying silicon layer. By this approach, the crystalline defect structure and the dopant distributions of the islands are individually optimized for specific applications.

REFERENCES:
patent: 4385937 (1983-05-01), Ohmura
patent: 4498224 (1985-02-01), Maeguchi
patent: 4509990 (1985-04-01), Vasudev
patent: 4523963 (1985-06-01), Ohta et al.
patent: 4584026 (1986-04-01), Wu et al.
patent: 4588447 (1986-05-01), Golecki
patent: 4617066 (1986-10-01), Vasudev
Reedy et al, Jour. Crystal Growth, 58 (1982) 53.
Yoshii et al, Jap. Jour. Appl. Phys. 21 (1982) Supplement 21-1, p. 175.
Yamamoto et al, Appl. Phys. Letts. 34(6), Mar. 1979, p. 403.
Lau et al, Appl. Phys. Letts. 34 (1979) 76.

Affiliated with

Also associated with

Rating

Selective area double epitaxial process for fabricating silicon- does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selective area double epitaxial process for fabricating silicon-, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective area double epitaxial process for fabricating silicon- will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-749458