Selection of divisor multipliers in a floating point divide circ

Details Selection of divisor multipliers in a floating point divide circ Selection of divisor multipliers in a floating point divide circ

1989-04-17

1991-02-26

Shaw, Dale M.

Boots, shoes, and leggings

364761, G06F 738

Patent

active

049966600

ABSTRACT:
A multiple selector logic circuit for selecting divisor multiples in 2-bit, non-restoring divide sequences, which provides a proper and accurate quotient result and remainder, and which produces rounding and indication of exact or inexact result in conformance with ANSI/IEEE Standard 754-1985; the multiple selector logic circuit incorporates semiconductor circuits including a multiplier table having a particular matrix of multipliers which meet the standard.

REFERENCES:
patent: 4320464 (1982-03-01), Desmonds
patent: 4722069 (1988-01-01), Ikeda
patent: 4724529 (1988-02-01), Irukulla et al.
Lemaire et al., "Improved Non-Restoring Division"IBM Tech. Discl. Bull. vol. 23, No. 3, Aug. 1980, pp. 1149-1151.
Basu et al., "On a Simple Post Correction for Non-Restoring Division" IEEE Trans. on Computers, Oct. 1975, pp. 1019-1020.
Sanyol, "An Algorithm for Non-Restoring Division" Computer Design, May 1977, pp. 124-125.

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