Selection circuit for three or four potentials

Details Selection circuit for three or four potentials Selection circuit for three or four potentials

1982-03-18

1985-02-12

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307473, 307585, H03K 19094, H03K 1920

Patent

active

044993889

ABSTRACT:
In order to obtain a low as possible generator internal resistance, a first inverter (IV1) is arranged between the first and the third potential (U1, U3), and the switching section of a second inverter (IV2) is connected to the zero point of the circuit and to the output of the first inverter (IV1) which is modified in such a way that between the switching sections of its two transistors (T21, T22) there is inserted an intermediate transistor (MT). The point connecting the switching sections of the intermediate transistor (MT) and of the other transistor (T22) of the second inverter (IV2) is the output of the selection circuit and is arranged, via the switching section of an additional transistor (ZT) to the second potential (U2). A first or a second selection signal (a, b) is applied to the input of the first or a second inverter (IV1, IV2) and a third selection signal (c) is applied to the gates of the intermediate and the additional transistor (MT, ZT), with the following Boolean logic functions applying to said third selection signal (c):

REFERENCES:
patent: 3936676 (1976-02-01), Fujita
patent: 4038564 (1977-07-01), Hakata
patent: 4309701 (1982-01-01), Nishimura
patent: 4324991 (1982-04-01), Tamaki
patent: 4408135 (1983-10-01), Yuyama et al.

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