Selection circuit for accurate memory read operations

Details Selection circuit for accurate memory read operations Selection circuit for accurate memory read operations

2003-02-10

2004-07-27

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250, C365S203000

Reexamination Certificate

active

06768679

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to semiconductor memory devices.
BACKGROUND ART
Memory devices are known in the art for storing data in a wide variety of electronic devices and applications. Electronic memory, for example, is widely used in a variety of commercial and consumer electronic products. A typical memory device comprises a number of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit. For example, a memory cell may be defined as either being a “programmed” cell or an “erased” cell. According to one particular convention, a programmed cell is representative of a “0” bit, and an erased cell is representative of a “1” bit. In one type of memory cell, each cell stores two binary bits, a “left bit” and a “right bit.” The left bit can represent a “0” or a “1” while the right bit can represent a “0” or a “1” independent of the left bit.
Typically, the state of a memory cell is determined during a read operation by sensing the current drawn by the memory cell. For example, to ascertain the current drawn by a particular memory cell, the drain terminal of the memory cell is connected to a sensing circuit, the source terminal of the memory cell is connected to ground, and the gate of the memory cell is selected. The sensing circuit attempts to detect the current drawn by the memory cell, and compares the sensed memory cell current against a reference current. If the sensed memory cell current exceeds the reference current, the memory cell is considered an erased cell (corresponding to a “1” bit). However, if the sensed memory cell current is below the reference current, the memory cell is considered a programmed cell (corresponding to a “0” bit).
In practice, it is desirable to have the sensed memory cell current be greater than or less than the reference current by a “read margin.” In the present application, read margin is defined as the absolute value of the difference between current drawn by a target memory cell and the current drawn by a reference cell during a read operation. With a sufficient read margin, the impact of extraneous factors, such as noise, for example, upon the detection of the memory cell current is greatly reduced. For instance, suppose the reference current used for comparison is fifteen (15) microAmps (&mgr;A) in a particular memory device. In this case, it would be desirable to sense a memory cell current of twenty (20) &mgr;A or greater for an erased cell (corresponding to a “1” bit) and a memory cell current of ten (10) &mgr;A or less for a programmed cell (corresponding to a “0” bit). With a five (5) &mgr;A read margin, the impact of extraneous factors, such as noise, is significantly reduced.
Conventional memory selection circuits, however, considerably reduce the read margin for sensing memory cell current during read operations (in the present application, reduction of the read margin is also referred to as “read margin loss”). When the read margin is significantly reduced, the reliability of sensing the memory cell current also decreases, since extraneous factors, such as noise, have a greater impact. The reliability of the read operation is thus reduced, resulting in poor performance of the memory device. Accordingly, there exists a strong need in the art to overcome deficiencies of known memory selection circuits and to provide a memory selection circuit and technique which results in reduced read margin loss in a fast and accurate manner during memory read operations.
SUMMARY
The present invention is directed to a selection circuit for accurate memory read operations. The invention addresses and resolves the need in the art for a selection circuit which results in reduced read margin loss in a fast and accurate manner during memory read operations. According to one exemplary embodiment, the selection circuit for sensing current in a target cell during a memory read operation comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. In the exemplary embodiment, the ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell. Each of the target cell and the first neighboring cell comprises a respective gate terminal connected to a common word line. In some embodiments, the target cell may also store a first bit and a second bit.
According to another exemplary embodiment, the sensing circuit selector connects a fourth bit line of a second neighboring cell to the sensing circuit during the read operation. In this particular embodiment, the second neighboring cell is adjacent to the first neighboring cell and shares the third bit line with the first neighboring cell. According to another exemplary embodiment, the selection circuit further comprises a precharge circuit selector connected to a precharge circuit. In this particular embodiment, the precharge circuit selector connects a fifth bit line of a third neighboring cell to the precharge circuit during the read operation. The third neighboring cell is adjacent to the second neighboring cell and shares the fourth bit line with the second neighboring cell.
According to another exemplary embodiment, the precharge circuit selector further connects a sixth bit line of a fourth neighboring cell to the precharge circuit during the read operation. In this particular embodiment, the fourth neighboring cell is adjacent to the third neighboring cell and shares the fifth bit line with the third neighboring cell. According to another exemplary embodiment, the precharge circuit selector connects a seventh bit line of a fifth neighboring cell to the precharge circuit during the read operation. In this particular embodiment, the fifth neighboring cell is adjacent to the fourth neighboring cell and shares the sixth bit line with the fourth neighboring cell.
According to another exemplary embodiment, the ground selector connects an eighth bit line of a sixth neighboring cell to ground during the read operation. In this particular embodiment, the sixth neighboring cell is adjacent to the target cell and shares the first bit line with the target cell. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.


REFERENCES:
patent: 6525969 (2003-02-01), Kurihara et al.
patent: 6529412 (2003-03-01), Chen et al.
patent: 2003/0156457 (2003-08-01), Ooishi

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