Selecting phase assignments for candidate nodes in a logic netwo

Details Selecting phase assignments for candidate nodes in a logic netwo Selecting phase assignments for candidate nodes in a logic netwo

1996-12-10

1999-05-11

Teska, Kevin

Boots, shoes, and leggings

364489, 364490, 364491, 364578, G06F17/50

Patent

active

059034670

ABSTRACT:
In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.

REFERENCES:
patent: 3643861 (1972-02-01), Eckerlin
patent: 3698632 (1972-10-01), Eckerlin
patent: 4631424 (1986-12-01), Miyagi
patent: 4868773 (1989-09-01), Coyle et al.
patent: 5477164 (1995-12-01), Denker
patent: 5508937 (1996-04-01), Abato et al.
patent: 5522063 (1996-05-01), Ashar et al.
patent: 5638380 (1997-06-01), De

Affiliated with

Also associated with

Rating

Selecting phase assignments for candidate nodes in a logic netwo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selecting phase assignments for candidate nodes in a logic netwo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selecting phase assignments for candidate nodes in a logic netwo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-250388