Selecting circuit including circuits having different time const

Details Selecting circuit including circuits having different time const Selecting circuit including circuits having different time const

1995-06-05

1998-02-10

Mai, Tan V.

Boots, shoes, and leggings

G05F 750

Patent

active

057176221

ABSTRACT:
A selecting circuit is formed of two tristate gates. The size of each of a plurality of transistors configuring a tristate gate processing a signal having a shorter delay time is set smaller than the size of each of a plurality of transistors configuring a tristate gate processing a signal having a longer delay time, so that the capacitance of the former transistors is decreased. As a result, the load to be driven by each of transistors to which a signal having a longer delay time is applied is decreased, whereby the entire circuit can be increased in operation speed. Accordingly, the selecting circuit selecting between two or more input signals having different delay times can operate at a high speed.

REFERENCES:
patent: 4683548 (1987-07-01), Mlynek
patent: 5231318 (1993-07-01), Reddy
"Principles of CMOS VLSI Design a Systems Perspective", By Addison-Wesley Publishing Company, Neil Weste et al.

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