Selectable write precompensation in a direct access storage devi

Details Selectable write precompensation in a direct access storage devi Selectable write precompensation in a direct access storage devi

1997-10-09

2000-03-28

Kim, W. Chris

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Pulse crowding correction

G11B 509

Patent

active

060439424

ABSTRACT:
A method and apparatus for write precompensation in a direct access storage device are provided. A data write encoder generates a data signal to be written. A write precompensation delay circuit is coupled to the data encoder for receiving and delaying the data signal. The write precompensation delay circuit includes a first delay path and a second delay path in parallel with the first delay path. The first delay path and the second delay path have different delay values. In one arrangement, both the first delay path and the second delay path include a plurality of delay cells connected together in a chain. The delay cells of the first delay path have a first predetermined delay value and the delay cells of the second delay path have a second predetermined delay value. A ratio of the second predetermined delay value to the first predetermined value is set equal to one of approximately 3/2, 4/3, 5/4, 6/5, or 7/6. In another arrangement, a first delay path includes a plurality of delay cells connected together in a chain and a plurality of delay cells connected in parallel provide multiple parallel delay paths.

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Philpott et al., "A 7 MB/Sec (65 Mhz), Mixed Signal, Magnetic Recording Channel DSP Using Partial Response Signalling With Maximum Likelihood Detection," IEEE Custom Integrated circuits Conference, 1993, pp. 10.4.1-10.4.4.

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