Selectable timing delay circuit

Details Selectable timing delay circuit Selectable timing delay circuit

1986-12-10

1989-02-14

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

375118, 370108, 328 63, H04L 702, H04J 306

Patent

active

048051950

ABSTRACT:
Disclosed is a programmable timing delay circuit for use in a synchronous system which includes a number of remote modules which must receive a synchronized clock in order to operate properly. The programmable timing delay circuit includes a plurality of delay paths which receive the reference clock signal and provide a variety of delays to a selector. The selector is controlled by an input means which allows selection of the optimum delay paths for a particular module. In this manner the clock signal received at each of the remote modules can be tuned to the desired synchronous phase.

REFERENCES:
patent: 2779933 (1957-01-01), Bradburd
patent: 3306978 (1967-02-01), Simmons et al.
patent: 4165490 (1979-08-01), Howe, Jr. et al.
patent: 4573173 (1986-02-01), Yoshida

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