Selectable-tap equalizer

Pulse or digital communications – Equalizers

Reexamination Certificate

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C375S232000, C375S296000

Reexamination Certificate

active

10195129

ABSTRACT:
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

REFERENCES:
patent: 4359778 (1982-11-01), Lee
patent: 4581747 (1986-04-01), Prezas et al.
patent: 5353147 (1994-10-01), Grimes
patent: 5659581 (1997-08-01), Betts et al.
patent: 5691993 (1997-11-01), Fredrickson
patent: 6340098 (2002-01-01), Drost et al.
patent: 6344749 (2002-02-01), Williams
patent: 6530062 (2003-03-01), Liaw et al.
patent: 6563870 (2003-05-01), Schenk
patent: 6687311 (2004-02-01), Zhang
patent: 6970049 (2005-11-01), Hipp
patent: 2001/0026595 (2001-10-01), Dally
patent: 2002/0181360 (2002-12-01), Hamada et al.
patent: 43 20 930 (1995-01-01), None
patent: 0 094 624 (1983-11-01), None
patent: 0 463 316 (1992-01-01), None
patent: 0 482 392 (1992-04-01), None
patent: 0 490 504 (1992-06-01), None
patent: 54051343 (1979-04-01), None
patent: 52127887 (1979-05-01), None
patent: 56164650 (1981-12-01), None
patent: 58-54412 (1983-03-01), None
patent: 56168711 (1983-04-01), None
patent: 59036465 (1984-02-01), None
patent: 60087551 (1985-05-01), None
patent: 60191231 (1985-08-01), None
patent: 60194647 (1985-10-01), None
patent: 0 352 860 (1990-01-01), None
patent: 02128201 (1990-05-01), None
patent: 02140676 (1990-05-01), None
patent: 04044691 (1992-02-01), None
patent: 05143211 (1993-06-01), None
patent: 08202677 (1996-08-01), None
patent: 08286943 (1996-11-01), None
patent: 09181778 (1997-07-01), None
patent: 10200345 (1998-07-01), None
patent: WO95/31867 (1995-11-01), None
patent: WO96/31038 (1996-10-01), None
patent: WO98/33306 (1998-07-01), None
patent: WO99/10982 (1999-03-01), None
S. A. Raghavan, J. K. Wolf, L. B. Milstein, and L. C. Barbosa, “Nonuniformly Spaced Tapped-Delay-Line Equalizers,” IEEE Transactions on Communications, vol. 41, No. 9, Sep. 1993, pp. 1290-1295.
S. Ariyavisitakul and L. J. Greenstein, “Reduced-Complexity Equalization Techniques for Broadband Wireless Channels,” IEEE Journal on Selected Areas in Communications, vol. 15, No. 1, Jan. 1997, pp. 5-15.
S. Ariyavisitakul, N. R. Sollenberger, and L. J. Greenstein, “Tap-Selectable Decision-Feedback Equalization,” IEEE Transactions on Communications, vol. 45, No. 12, Dec. 1997, pp. 1497-1500.
IEEE Standard 802. 3ad-1999, 802.3 Supplement, Local and Metropolitan Area Networks. Jul. 17, 1999.
802.3ab, A Tutorial Presentation, 63 pages, undated, believed by applicants to have been presented at an IEEE 80.3 working group meeting in Mar. 1998.
Thompson “How 1000Base-T Works,” IEEE802.3 Plenary, Nov. 1997, Montreal PQ Canada, 8 pages.
Perez-Alvarez et al. “A Differential Error Reference Adaptive Echo Canceller for Multilevel PAM Line Codes,” 0-7803-3192-3/96, IEEE, 1707-1710.
Kuczynski et al., “A 1 Mb/s Digital Subscriber Line Transceiver Signal Proccese,” 1993 IEEE International Solid State Circuit Conference.
S.D. Cova et al., “Characterization of Individual Weights in Transversal Filters and Application to CCD's” IEEE Journal of Solid-State Circuits, vol. SC-17, No. 6, Dec. 1982.
Dally et al., “Multi-Gigabit Signaling with CMOS.,” May 12, 1997.
Fielder, et al. “A 1.0625 Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis,” 1997 IEEE International Solid State Circuit Conference and Slideset.
Sidiropoulos, Stefanos, et al. “A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers,” IEEE Journal of Solid-State Circuits; vol. 32, No. 5, May 1997; pp. 681-690.
Donnelly, Kevin et al. “A 660 MB/s Interface Megacell Portable Circuit in .3 •m-.7•m CMOS ASIC”, IEEE Journal of Solid State Circuits; vol. 31, No. 12; Dec. 1996, pp. 1995-2003.
Allen, Arnold O., “Probability, Statistics and Queueing Theory with Computer Science Applications,” 2nd Edition, CH 7; pp. 450, 458-459.
Chappell, Terry et al. “A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM”, IEEE International Solid State Circuits Conference 1991; pp. 50-51.
Pilo, Harole et al., “A 300 MHz 3.3V 1 Mb SRAM Fabricated in a .5 •m CMOS Process”, IEEE International Solid State Circuits Conference 1996; pp. 148-149.
Schumacher, Hans-Jurgen et al., “CMOS Subnanosecond True-ECL Output Buffer”, IEEE Journal of Solid-State Circuits, vol. 25, No. 1; Feb. 1990 pp. 150-154.
Yang, Tsen-Shau et al., “A 4-ns 4Kx1-bit Two-Port BiCMOS SRAM”, IEEE Journal of D-State Circuits; vol. 23, No. 5; Oct. 1988; pp. 1030-1040.
Sidiropoulos, Stefanos, et al. “A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers,” IEEE VLSI Circuits Symposium, 1996; pp. 142-143.
Bazes, “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers”, IEEE Journal of Solid State Circuits, vol. 26 No. 2, Feb. 1991.
Ishibe et al., “High-Speed CMOS I/O Buffer Circuits”, IEEE Journal of Solid State Circuits, vol. 27, No. r, Apr. 1992.
Lee et al., “A 80ns 5v-Only Dynamic RAM”, ISSCC proceedings, Paper 12.2 ISSCC 1979.
Seki et al., “A 6-ns 1Mb CMOS SRAM with Latched Sense Amplifier”, IEEE Journal of Solid State Circuits, vol. 28, No. 4., Apr. 1993.
Kobayashi et al. “A current-controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Pressure Architecture”, IEEE Journal of Solid State Circuits vol. 28 No. 4., Apr. 1993.
Tomassini et al. “A fully differential CMOS Line Driver for ISDN”, IEEE Journal of Solid State Circuits, vol. 25, No. 2., Apr. 1990.
Farjad-Rad et al., A .4 •M CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter:, IEEE Journal of Solid State Circuits, vol. No. 34, pp. 580-585, May 1999.
Yeung et al., “A 2.4Gbps per pin Simultaneous Bidirectional Parallel Link With per pin Skew Calibration”, ISSCC 2000, in press as of Jan. 9, 2000.
Portmann et al., “A Multiple Vendor 2.5-V DLL for 1.6-GB/s RDRaMs”, IEEE VLSI Circuits Symposium, Jun. 1999.
Moncayo et al., Bus Design and Analysis at too MHz and Beyond:, Presented at the Design SuperCon, 1995.
Lau et al. “A 2.6-Gbyte/s Multipurpose Chip-to-Chip Interface”, IEEE J. Solid-State Circuits, vol. 33, pp. 1617-1626, Nov. 1998.
Current, 1994, “Current-Mode CMOS Multiple-Valued Logic Circuits,” IEEE Journal of Solid-State Circuits 20 (2): 95-107.
Dally and Poulton, Digital System Engineerings, Cambridge University Press, New York, N, 1998 pp. 344-347 and 352.
Farjad-Rad et al., “An Equalization Scheme for 10Gb/s 4-PAM Signaling Over Long Cables,”Presentation Center for Integrated Systems, Department of Electical Engineering, Stanford University, Jul. 28, 1997.
Farjad-Rad et al., 1999, “A .4-•m CMOS 10-GB/s 4-PAM Pre-Emphasis Serial Ling Transmitter,” IEEE Journal of Solid-State Circuits 34(5):580-585.
IBM Technical Disclosure Bulletin, Jun. 1967, “Use of Multibit encoding to Increas Linear Recording Densities in Serially Recorded Records,” pp. 14-15.
IBM Technical Disclosure Bulletin, Jan. 1968, “Coding Data Transmission,” pp. 1295-1296.
IBM Technical Disclosure Bulletin, Jul. 1969, “Clock Recovery Circuit,” pp. 219-220.
IBM Technical Disclosure Bulletin, Nov. 1970, “Transmission by Data Encoding,” pp. 1519-1520.
IBM Technical Disclosure Bulletin, Feb. 1976, “Bidirectional Communica

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