Optical: systems and elements – Deflection using a moving element – Using a periodically moving element
Reexamination Certificate
1999-10-28
2002-10-08
Chan, Jason (Department: 2633)
Optical: systems and elements
Deflection using a moving element
Using a periodically moving element
C359S199200, C359S199200, C326S115000, C326S127000, C326S082000
Reexamination Certificate
active
06462852
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to the field of data communications, and in particular, to facilitating integrated circuit-to-integrated circuit (IC-IC) differential communication involving integrated circuits having different logic topologies, by providing the ability to accept two or more different input/output (I/O) signal voltage levels, which are either direct coupled or AC coupled therewith.
BACKGROUND INFORMATION
With the increasing needs for communication between IC's at relatively high data rates, e.g., data rates of above 1.0 Gigabits/second, the use of differential signals is becoming increasingly popular. One reason is because the reduced voltage swings of differential signals increase the achievable maximum data rate. Also, inherent characteristics, such as lower self generated switching noise, reduced electromagnetic interference (EMI), better input noise rejection and power supply rejection, are attractive features of logic having a so-called ‘differential topology’.
Particularly in the field of telecommunications, bipolar CML (current mode logic) or PECL (positive emitter-coupled logic) are preferred, due to higher speed, lower skew, and less jitter than a low-voltage differential signal (LVDS), self-timed interface (STI), or dynamic CMOS (complimentary metal oxide semiconductor) design.
However, one problem for the designer is that these differential logic families which are currently popular, are not compatible with each other because of t e different voltage levels used to represent the same logic level!.
By way of explanation, integrated circuitry in the emitter-coupled logic (ECI) family uses bipolar-transistors and has the advantages of being very fast, having high input resistance, having low output resistance, and having low noise generation. However, ECL logic signal levels, referenced to a power supply voltage terminal commonly labeled VCC, are approximately (VCC−VBE) for a logic high voltage, and (VCC−
2
VBE) for a logic low voltage, where VBE is the forward biased base-emitter diode voltage drop of a corresponding bipolar transistor. With ECL, in order to provide the logic high voltage (VCC−VBE), however, an extra transistor is necessary. A similar type of logic using bipolar transistors, known as current-mode logic (CML), eliminates the need for an extra transistor by providing a logic high voltage of VCC, and a logic low voltage of approximately (VCC−VBE). The output level is thus more constrained but in many cases the saving of a transistor is advantageous.
Presently, metal oxide semiconductor (MOS) transistors are commonly fabric ted in integrated circuits along with bipolar transistors. As a result, some logic circuits providing CML level output signals are required to receive at least one input signal compatible with the MOS transistors in addition to receiving at least one CML level input signal.
However, complementary metal oxide semiconductor (CMOS) signal levels differ from ECL. and CML signal levels. In so-called full-swing CMOS signals, a logic high voltage is approximately VCC, whereas a logic low voltage is approximately a second power supply voltage, commonly labeled “VSS”, which is negative with respect to VCC. As can be appreciated, when CMOS levels are applied to a base of a bipolar transistor in a CML logic circuit, reliability problems can result because of the differences in logic level voltages.
For example, a large reverse bias, which occurs if a CMOS logic low voltage (about VSS) is applied to the base of an input bipolar transistor while the emitter is held at or near a CML logic high voltage (VCC−VBE), is harmful to the operation of the input bipolar transistor. When a large reverse bias is applied across the base-emitter junction of a bipolar transistor, degradation occurs. Over time, the constant application of this large reverse bias may cause the input bipolar transistor to fail, resulting in a failure of the entire integrated circuit. Electronically, a large reverse bias on a PN junction causes hot carrier injection into the overlying oxide, resulting in poor junction performance. The amount of hot carrier injection is proportional to the time the reverse bias occurs. The size of the reverse bias is related to the mean life of the transistor, for given worst case conditions, by an inverse semi-logarithmic relationship. As the reverse bias decreases linearly, mean life increases exponentially. At typical values for reverse bias, transistor mean life in a mixed CML and CMOS logic circuit may be unacceptably short.
Therefore, full-swing CMOS can damage bipolar circuitry. However, Seven low-voltage differential signal (LVDS) CMOS signals can cause problems with bipolar circuitry, and the low signal levels may not be able to drive the bipolar circuitry.
There may be places in the data communication industry, for example, where a CMOS input/output design is preferred over a bipolar one, e.g., in a computer interface whose CMOS outputs swing rail-to-rail (+VCC to VSS=−VCC), or even in lower-voltage signals where the voltage swings around 1.25 volts by plus and minus 0.50 volts, i.e., between 1.75 and 0.75 volts. Thus, there may be situations where either or both CMOS and bipolar signal levels need to be accommodated.
Because of the present need for both CMOS and bipolar communications, an IC manufacturer currently may have to provide for both CMOS and bipolar communications technologies in different products, or in the same product. Clearly, for the chip manufacturer, it would be advantageous to have a single chip design which accommodates both types of receivers.
A possible solution considered by the inventors would be to provide a design in which one integrated circuit chip has both types of receivers on-board, either of which can be selected during manufacture by metal masking, for example, depending on which technology (CMOS or bipolar) is to be supported in the finished chip. However, a disadvantage of this solution is that the product user would still have to purchase both species of the chip to accommodate a design that uses both technologies. A further disadvantage is the cost of the separate metal mask, and another disadvantage is the time and cost of qualifying two parts.
Another solution considered by the inventors is to have both types of receivers integrated in the finished chip and fully operational with their own separates inputs. However, this solution disadvantageously doubles the differential receiver input pin-out increasing costs.
Therefore, the above-described possible solutions are disadvantageous because of the cost of two chips, the cost of a separate metal mask, and/or the increased pin-out requirement for the package. These disadvantages make these solutions less than optimal.
It would be desirable to be able to accommodate both technologies with one receiver chip without requiring masking or increasing the pin-out.
Therefore, a need exists for an optimal solution to the problem of accommodating both CMOS and bipolar technologies in a single chip (IC) which can receive (and/or send) two different input/output levels, without the disadvantages of the other above-mentioned possible solutions.
U.S. Pat. No. 5,283,482 by Chen, issued Feb. 1, 1994, describes (Abstract) a CMOS circuit for receiving ECL signals which includes a triple-feedback arrangement for dynamically biasing a current source transistor of a differential amplifier of the CMOS circuit. The CMOS receiver circuit has a differential amplifier for generating an output signal representative of the difference between a reference signal and an ECL input signal, and an inverter circuit for receiving the output signal and generating a CMOS compatible output signal. The differential amplifier includes a first current source transistor. A first CMOS transistor is connected to receive the ECL input signal and a second CMOS transistor is connected to receive the reference signal. The first and second CMOS transistors have their drains coupled to first a
Demsky Kevin Paul
Paschal Matthew James
Bussan Matthew J.
Chan Jason
Lynt Christopher H.
Sedighian M. R.
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