Communications: electrical – Selective – Decoder matrix
Reexamination Certificate
1999-10-28
2003-06-17
Pope, Daryl (Department: 2735)
Communications: electrical
Selective
Decoder matrix
C365S200000, C365S233100, C326S027000, C326S083000, C370S413000
Reexamination Certificate
active
06580359
ABSTRACT:
FIELD OF INVENTION
This invention relates to a selectable input buffer control system.
BACKGROUND OF INVENTION
Buffer circuits are wisely used in analog and digital circuits to broadcast a signal to one or more receiver circuits which may be as simple as a point cell in a crosspoint circuit or as complex as a microprocessor. The buffers may serve several purposes: restoring logic levels, providing gain, level shifting, etc. However, one of the most important functions of the buffers is to isolate the source from input admittance (usually capacitive) of the receivers and the wires leading to them by providing a unilateral signal path, usually with high input impedance and low output impedance. An important disadvantage of the buffers is their power consumption.
Prior art crosspoint switches often employ some form of input buffer to isolate the external input signals from the input busses in both analog and digital implementations. At its core is an array of point cells, in which each row constitutes a multiplexer. A separate latch drives the address bus of each row and these address lines are connected to the local decoding circuitry within each point cell in such a way as to ensure that at most one point cell in a row is enabled at any time. The outputs of the points in each row are connected to an output buffer which drives the external load. Input busses, each driven by an input buffer, are connected to the input terminals of the point cells in their respective columns. All input buffers in this architecture are always (regardless of the state of the crosspoint matrix) enabled and dissipating power to drive replicas of their input signals onto their respective input busses. Some prior art crosspoint switch implementations save power and area by omitting the input buffers. Since the input resistance of the point cells is relatively high (several M&OHgr;), matching to the source is typically achieved using an off-chip termination resistor to ground.
One prior art digital crosspoint switch uses the distributed inductance of the input bus in conjunction with its distributed capacitance and the input capacitance of the point cells to form a transmission line which is an extension of the transmission line feeding the crosspoint chip. The geometry of the input bus line is adjusted to match its characteristic impedance to that of the off-chip line. Although impedance discontinuities may exist at the chip interface due to package parasitics, reflections at the end of the on-chip line are minimized by an on-chip termination resistor. By controlling the impedance of the input bus and terminating it, this technique mitigates the effects of the on-chip input bus capacitance without buffers. On-chip transmission lines with on-chip termination resistors have a number of shortcomings. The on-chip resistor uses a substantial amount of power; it requires another on-chip component and the fabrication process produces a ±10% or even ±20% variation in the resistance value. Further, that resistance is fixed and cannot match the different characteristic impedances of the various input lines to which it may be connected. In addition, in applications where internal termination resistors are used in each cross-point circuit, the biasing of an input to more than one cross-point circuit causes a serious impedance mismatch because of the paralleling of all of the termination resistors.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved selectable input buffer control system
It is a further object of this invention to provide such an improved selectable input buffer control system which uses less power.
It is a further object of this invention to provide such a selectable input buffer control system which enables an input buffer to broadcast only if at least one of its receivers is listening.
It is a further object of this invention to provide such a selectable input buffer control system which provides all the advantages of buffered input systems, e.g., lower input capacitance, higher input sensitivity, controlled source impedance, controlled common-mode levels, small lower power equalized logic swings, but reduces required power and cross talk.
The invention results from the realization that an improved selectable input buffer control system which reduces power requirements and cross-talk can be effected with a selector circuit associated with each of one or more input buffers for enabling the associated input buffer in response to the addressing of any one or more of the input receivers associated with that input buffer.
This invention features a selectable input buffer control system including a plurality of input receivers arranged in rows and columns and a number of input buffers, one associated with each column, for driving input receivers in that column. There is an address circuit for addressing each input receiver in a row. A selection circuit is associated with each input buffer for enabling its associated input buffer in response to the addressing of any one or more of the input receivers in that column associated with that input buffer.
In a preferred embodiment the selection circuit may include a single control conductor between the input receivers and their associated input buffer. Each input buffer may include a driver circuit. Each selection circuit may include a disabling signal source for disabling the driver of the associated input buffer and a switching device in each of the input receivers associated with that driver for overriding the disabling that driver when one or more of the input receivers associated with that driver has been addressed. Each selection circuit may include a disabling signal source for disabling the driver of the associated input buffer, a switched current source in each of the input receivers associated with that driver for overriding the disabling signal and enabling that driver when one or more of the input receivers associated with that driver has been addressed. Each selection circuit may include a current sensing circuit for sensing the total current in the selection circuit and adjusting the output resistance of that driver in inverse proportion to the number of associated input receivers addressed to maintain a stable RC constant and propagation delay.
The invention also features a selectable input buffer control system including at least one input buffer and a plurality of input receivers associated with each input buffer. There is an address bus for addressing each input receiver and a selection circuit associated with each of the input buffers for enabling its associated input buffer in response to the addressing of any one or more of the input receivers associated with that input buffer.
In a preferred embodiment the selection circuit may include a single control conductor between the input receivers and their associated input buffer. Each input buffer may include a driver circuit. Each selection circuit may include a disabling signal source for disabling the driver of the associated input buffer and a switching device in each of the input receivers associated with that driver for overriding the disabling that driver when one or more of the input receivers associated with that driver has been addressed. Each selection circuit may include a disabling signal source for disabling the driver of the associated input buffer, a switched current source in each of the input receivers associated with that driver for overriding the disabling signal and enabling that driver when one or more of the input receivers associated with that driver has been addressed. Each selection circuit may include a current sensing circuit for sensing the total current in the selection circuit and adjusting the output resistance of that driver in inverse proportion to the number of associated input receivers addressed to maintain a stable RC constant and propagation delay.
REFERENCES:
patent: 5245585 (1993-09-01), Voss et al.
patent: 5315174 (1994-05-01), Chang et al.
patent: 5541535 (1996-07-01), Cao et al.
patent: 5544104
Analog Devices Inc.
Iandiorio & Teska
Pope Daryl
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