Selectable edge rate CMOS output buffer circuit

Details Selectable edge rate CMOS output buffer circuit Selectable edge rate CMOS output buffer circuit

1991-10-03

1993-06-08

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307263, 307542, 307599, H03K 1716, H03K 1920

Patent

active

052182398

ABSTRACT:
CMOS output circuit improvements control output signal rise and fall times during transition between high and low potential levels at the output (V.sub.OUT). A plurality of pulldown predriver resistors (R1.sub.N, R2.sub.N, R3.sub.N) are coupled in parallel paths in the pulldown predriver circuit. Respective resistance values slow turn on of the output pulldown driver transistor (N1) for achieving a plurality of different fall times. A plurality of pulldown predriver switch transistors (PS1, PS2, PS3) are respectively coupled in series with the pulldown predriver resistors (R1.sub.N, R2.sub.N, R2.sub.N). The switch transistors (PS1, PS2, PS3) have respective control inputs (V.sub.S1, V.sub.S2, V.sub.S3) for selecting respective parallel paths containing the different pulldown predriver resistors (R1.sub.N, R2.sub.N, R3.sub.N). A plurality of pullup predriver resistors (R1.sub.P, R2.sub.P, R3.sub.P) are coupled in parallel paths in the pullup predriver circuit. Respective resistance values slow turn on of the output pullup driver transistor (P1) for achieving a plurality of different rise times. A plurality of pullup predriver switch transistors (NS1, NS2, NS3) are coupled respectively in series with the pullup predriver resistors (R1.sub.P, R2.sub.P, R3.sub.P). The switch transistors (NS1, NS2, NS3) are coupled to the respective switch transistor control inputs (V.sub.S1, V.sub.S2, V.sub.S3) for selecting respective parallel paths of the pullup predriver resistors (R1.sub.P, R2.sub.P, R3.sub.P). Different rise and fall times are selected by digital addressing for the output signal transitions between low to high potential levels at the output (V.sub.OUT).

REFERENCES:
patent: 4751410 (1988-06-01), Tanizawa
patent: 4827159 (1989-05-01), Naganuma
patent: 4906867 (1990-03-01), Petty
patent: 4924120 (1990-05-01), Schenck
patent: 4961010 (1990-10-01), Davis
patent: 4985646 (1991-01-01), Kumagi
patent: 5010256 (1991-04-01), Dicke
patent: 5036222 (1991-07-01), Davis
patent: 5049763 (1991-09-01), Rogers
U.S. Patent Application Ser. No. 483,927 filed Feb. 22, 1990 now Patent No. 5,081,374.

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