Coded data generation or conversion – Digital code to digital code converters – To or from nrz codes
Reexamination Certificate
2000-03-20
2001-06-05
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from nrz codes
C327S157000
Reexamination Certificate
active
06243031
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to circuits and methods for selectably delaying an input signal, and more particularly to such circuits and methods in which selected delay remains highly stable despite variations in fabrication, component matching, and operating temperature, and in which selectable delay facilitate write operations of consecutive data pulses to a magnetic storage medium in a manner that eliminates or reduces non-linear bit shifts.
2. Background of the Invention
Conventional magnetic storage devices typically read and write data onto one or more data tracks in a magnetic storage medium. In a conventional hard disk drive, for example, the data tracks are concentric rings on one or both surfaces of a hard disk or plurality of hard disks. To write data to a track, the disk is rotated at a determined rate of speed, and a magnetic read/write head floating over the track transforms electrical signals to magnetic transitions on the track.
Digital data is thus stored on conventional magnetic storage devices by encoding such data as the presence and absence of magnetic transitions or pulses. A pulse can represent a bit value of ONE, and the absence of a pulse can represent a ZERO. In another conventional technique (referred to Non-Return to Zero Inverted (NRZI) coding), a bit value of ONE is represented by a change or transition in magnetization orientation, and a bit value of ZERO is represented by the absence of such change or transition. Thus, in NRZI coding, a string of three ONES is represented by a storage pulse, followed by absence of a storage pulse, followed by a storage pulse.
Each storage pulse magnetizes a small magnetic domain on a track, and the magnetic intensity of such a stored pulse is typically wedge shaped with higher intensity at the center of the small domain than near the leading and trailing edges thereof. Locations of magnetic pulses and locations of absent pulses typically are positioned in very close proximity in each track. This can create storage errors if adjacent stored pulses overlap, and the data significance of overlapping stored pulses can be difficult to interpret. Two consecutively stored magnetic pulses can be misread as a single stored pulse. This effect is commonly referred to as intersymbol interference, and can account for a much higher percentage of total data storage errors than noise. Recording high densities of data on a magnetic medium can also result in data distortion due to pulse compression, pulse-edge displacement and non-linearities of the storage device.
One approach for reducing such known problems is to spread immediately sequential magnetic pulses over a slightly larger length of track. This produces a small gap between the sequential pulses, and thus reduces intersymbol interference. The gap commonly used typically has a length that is shorter than the increment of track that represents absence of a stored pulse. Consequently, the gap can be distinguished from such absence. This conventional approach to reducing intersymbol interference is commonly called write precompensation.
Conventional write precompensation circuits and methods commonly determine write precompensation delays as integral numbers of clock cycles. Such circuits and methods require very high frequency clocking of components to provide appropriate write precompensation delays of very short duration. Other conventional circuits and methods require resistor and capacitor (RC) circuits to determine write precompensation delays. Such RC circuits tend to perform poorly because resistors and capacitors having sufficiently fine tolerances to provide accurate delays are difficult to fabricate, and the duration of delay provided by such RC circuits is thus typically not precisely defined. Further, the duration of delay provided by such RC circuits is often susceptible to variations in the operating temperature thereof.
SUMMARY OF THE INVENTION
In accordance with the present invention, high performance circuits and methods provide selectable delay of input signals, using a feedback loop to stabilize the duration of the delay provided. Each feedback loop receives a delay control signal for adjusting the duration of such delay over a range of values that can increase up to about ninety percent of the clock interval.
Specifically, a delay-locked loop generates an accurate delay of the master clock. A delay element converts the master clock to a controlled duty cycle clock that has one fixed clock edge and another trailing edge that is varied in time in response to programming control by as much as 90% of the master clock interval. The delayed clock edge provides the delayed reference clock to convert input NRZI data into delayed Non-Return to Zero (NRZ) data. The output of a first one of a plurality of identical delay elements serves as a reference, and the outputs of the remaining delay elements are variously delayed relative to the reference. Thus, an NRZ pattern of varied delays relative to the reference NRZ pattern is generated, and a control circuit selects the appropriate delayed NRZ data in accordance with past history of supplied NRZI data. In accordance with one embodiment of the invention, any one of four such delay elements is selected in response to at least two prior or previous intervals of NRZI data. Thus, the appropriate delayed NRZ data is selected via a multiplexer that is controlled in response to the NRZI data states in each of two prior delayed intervals. The requisite control circuits and delay elements thus function with high accuracy and substantial immunity from fabrication variations.
The delay elements according to one embodiment of the present invention each includes a detector, a charge-pump, and a capacitor connected in a feedback loop, with the detector generating the delayed clock signal in response to the state of the clock signal and an average voltage across the capacitor. The state of the delayed clock signal controls the direction of current supplied to the capacitor by the charge-pump and the amplitude of this current is controlled by the delay control signal. The charge-pump periodically charges and discharges the capacitor to produce a periodic time-varying voltage thereacross. The average value of this time-varying voltage determines duration of the delayed clock signal. For each delay element, the capacitor is repetitively charged and discharged in each cycle of the master clock signal to ensure settling to steady-state operating conditions when locked onto the selected duration of delay.
The high performance circuit of the present invention provides write precompensation for an input signal to be stored as NRZ encoded data. This high performance circuit compensates for various non-linearities in the storage device and storage process, and the durations of delays are selectable to avoid intersymbol interference.
REFERENCES:
patent: 4623805 (1986-11-01), Flora et al.
patent: 5159205 (1992-10-01), Gorecki et al.
patent: 5642068 (1997-06-01), Wojcicki et al.
patent: 5777567 (1998-07-01), Murata et al.
patent: 6133861 (2000-10-01), Jusuf et al.
Jusuf Gani
Sutardja Pantas
Fenwick & West LLP
Jean-Pierre Peguy
Marvell International Ltd.
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