Select line hold down circuit for MOS memory decoder

Details Select line hold down circuit for MOS memory decoder Select line hold down circuit for MOS memory decoder

1975-09-02

1977-03-08

Curtis, Marshall M.

Communications: electrical

Digital comparator systems

307205, 340173R, G11C 1144

Patent

active

040115496

ABSTRACT:
A decoder for a semiconductor MOS random access memory includes a dynamic NOR gate having a first output. The decoder also includes a selection MOSFET for providing a selection signal to a selection conductor connected to a row or column of an array of storage cells of said random access memory. The gate electrode of the selection MOSFET is connected to the output node of the NOR gate. The drain of the selection MOSFET is connected to a signal conductor adapted to having a signal applied thereto which is a function of a read/write signal applied to said random access memory. The source of the selection MOSFET is connected to the selection conductor. A feedback MOSFET is coupled between the output of the dynamic NOR gate and the selection conductor and has its gate electrode controlled by the signal which is a function of the read/write input signal. When the NOR gate is selected by a particular combination of address input variables, its initially precharged output node is discharged to ground. The feedback MOSFET discharges the selection conductor to ground through the feedback MOSFET and the combination of input MOSFETs of the NOR gate which previously discharged the output node thereof. The discharge of the selection conductor occurs when the read selection signal is applied to the gate of the feedback MOSFET.

REFERENCES:
patent: 3500062 (1970-03-01), Annis
patent: 3747076 (1973-07-01), Martino, Jr.
patent: 3876993 (1975-04-01), Cavanaugh

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