Communications: electrical – Digital comparator systems
Patent
1975-08-18
1977-02-08
Malzahn, David H.
Communications: electrical
Digital comparator systems
G06F 702
Patent
active
040074390
ABSTRACT:
In a large parallel processing environment including a plurality of active registers storing either normalized floating point or integer data a high/low register selection circuit identifies selectively the register or registers storing either the highest or lowest numerical data value. The numerical data in each active register is first converted into a pure binary magnitude pattern having the same relative value as the original numerical data for a select high register search, and the inverse relative value for a select low register search. Thereafter, the binary patterns from all active registers are processed together two bits at a time through an OR network with the OR network output functioning to deactivate all registers having an OR'ed two bit pattern less than the OR network output value. The deactivating process is continued two bits at a time until either only one register remains active or all bits have been processed two bits at a time through the OR network.
REFERENCES:
patent: 3731765 (1973-05-01), Robaszkiewicz
patent: 3825895 (1974-07-01), Larsen et al.
patent: 3829664 (1974-08-01), Kashio
K. E. Dimitri, "Dynamic Binary Word Comparator," IBM Technical Disclosure Bulletin, vol. 14, No. 8, Jan., 1972, pp. 2292-2293.
DiVecchio Mark Camillo
Semmelhaack Carl Frederick
Brenner L. C.
Burroughs Corporation
Chung E. M.
Malzahn David H.
Peterson K. R.
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