Seizing current delay circuit for the test switching means of a

Details Seizing current delay circuit for the test switching means of a Seizing current delay circuit for the test switching means of a

1977-12-22

1979-03-27

Cooper, William C.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307293, H04M 322

Patent

active

041467523

ABSTRACT:
A switching arrangement for a telecommunication switching system having test and seizing circuits is disclosed in which test switching means for bounce-free contact operation require a seizing current rise delayed by switching means in the seizing circuit. The improvement comprises a transistor for establishing the seizing current, a testing resistor disposed in series with the transistor and an RC network associated with the transistor. The potential across a control electrode of the transistor which is determined by the charging voltage of said associated RC network defines a control current. The potential renders the transistor increasingly conductive to current in accordance with a charging process setting in at the start of a test and seizing operation.

REFERENCES:
patent: 4041245 (1977-08-01), Konig et al.
patent: 4049922 (1977-09-01), Konig et al.

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